hankshyu / SnakeGameLinks
a verilog snake game program
☆10Updated 2 years ago
Alternatives and similar repositories for SnakeGame
Users that are interested in SnakeGame are comparing it to the libraries listed below
Sorting:
- 交通大學iclab 2023 fall☆42Updated 11 months ago
- 陽明交通大學/台灣大學 修課心得😀☆12Updated last year
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆136Updated last year
- ☆10Updated last year
- 紀錄一下自己寫過的所有Lab☆35Updated last year
- ☆13Updated 3 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南,含資源整理☆99Updated 5 months ago
- NYCU ICLAB 2025 spring codes & 心得☆15Updated 2 weeks ago
- ☆14Updated 4 years ago
- IC Contest☆41Updated 2 years ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆20Updated last year
- ☆27Updated 10 months ago
- MAC system with IEEE754 compatibility☆13Updated last year
- 交大電子所-積體電路實驗設計-李鎮宜教授☆13Updated last year
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆13Updated 2 years ago
- IC-contest 2012~2024☆20Updated last year
- Router 1x3 design and uvm verification testbach and coverage report☆12Updated 10 months ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆187Updated 2 years ago
- ☆16Updated last year
- ☆20Updated last year
- ☆10Updated last year
- ☆15Updated 2 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆14Updated last year
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Updated 8 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆21Updated last year
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆23Updated 8 months ago
- opensource EDA tool flor VLSI design☆34Updated 2 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆65Updated 2 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆25Updated 3 weeks ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆96Updated 2 years ago