hankshyu / SnakeGameLinks
a verilog snake game program
☆11Updated 3 years ago
Alternatives and similar repositories for SnakeGame
Users that are interested in SnakeGame are comparing it to the libraries listed below
Sorting:
- Hardware Description Language on FPGA☆10Updated 2 years ago
- ☆14Updated 4 years ago
- 陽明交通大學/台灣大學 修課心得😀☆13Updated last year
- [NYCU 2021 Spring] Digital Circuits and Systems☆22Updated last year
- Reference examples and short projects using UVM Methodology☆287Updated 3 years ago
- IC-contest 2012~2024☆21Updated last year
- Implementation of CNN using Verilog☆235Updated 8 years ago
- 交通大學iclab 2023 fall☆44Updated last year
- 100 Days of RTL☆403Updated last year
- Router 1x3 design and uvm verification testbach and coverage report☆12Updated last year
- ☆27Updated 3 months ago
- ☆14Updated 3 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆224Updated 7 months ago
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆153Updated last year
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Updated 8 years ago
- AMBA bus lecture material☆497Updated 5 years ago
- ☆185Updated 3 years ago
- training labs and examples☆443Updated 3 years ago
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆216Updated 2 years ago
- uvm AXI BFM(bus functional model)☆264Updated 12 years ago
- Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images☆66Updated 4 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆197Updated 2 years ago
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆302Updated last year
- Pipeline FFT Implementation in Verilog HDL☆153Updated 6 years ago
- Computer-Aided VLSI System Design☆23Updated last year
- 紀錄一下自己寫過的所有Lab☆38Updated last year
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆114Updated 11 years ago
- VIP for AXI Protocol☆163Updated 3 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆591Updated 4 years ago
- IC Contest☆42Updated 2 years ago