ekigwana / adi_dmac_iio_clientLinks
Client Driver for this HDL module: https://github.com/analogdevicesinc/hdl/tree/master/library/axi_dmac
☆15Updated 3 years ago
Alternatives and similar repositories for adi_dmac_iio_client
Users that are interested in adi_dmac_iio_client are comparing it to the libraries listed below
Sorting:
- The USRP™ Hardware Driver FPGA Repository☆293Updated 3 years ago
- RTL implementation of components for DVB-S2☆121Updated 2 years ago
- A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog☆210Updated 3 months ago
- AD9361 based USB3 SDR☆115Updated 7 years ago
- IIO AD9361 library for filter design and handling, multi-chip sync, etc.☆91Updated last month
- Zynq SoC Linux kernel driver for Xilinx AXI-Stream FIFO IP☆54Updated 6 months ago
- This is the Analog Devices Inc. Yocto/OpenEmbedded layer☆43Updated last week
- ANTSDR Firmware☆138Updated 2 years ago
- MATLAB toolbox for ADI transceiver products☆63Updated 5 months ago
- Open source Zynq timestamping implementation from Software Radio Systems (SRS)☆72Updated 2 years ago
- Python interfaces for ADI hardware with IIO drivers (aka peyote)☆186Updated last week
- PYNQ example of using the RFSoC as a QPSK transceiver.☆105Updated 2 years ago
- Design files for sdr5 prototype (Zynq + AD9363)☆106Updated 5 years ago
- Yocto Project BSPs for Ettus Products☆35Updated 6 months ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆115Updated last year
- IIO blocks for GNU Radio☆103Updated 2 years ago
- A configurable C++ generator of pipelined Verilog FFT cores☆246Updated last year
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆54Updated 8 years ago
- LTE Turbo Decoder using BCJR algorithm☆11Updated 7 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆59Updated 6 years ago
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆432Updated 2 years ago
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆119Updated last month
- The official Xilinx u-boot repository☆18Updated this week
- HDL code for a complex multiplier with AXI stream Interface☆13Updated 2 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆88Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆50Updated 2 years ago
- Enable your Pluto SDR to become a stand-alone OFDM transceiver with batman-adv mesh network routing capabilities☆125Updated 5 years ago
- Python productivity for RFSoC platforms☆79Updated 2 months ago
- DPLL for phase-locking to 1PPS signal☆32Updated 9 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆83Updated last year