defano / digital-design
An introduction to integrated circuit design with Verilog and the Papilio Pro development board.
☆14Updated 2 weeks ago
Alternatives and similar repositories for digital-design:
Users that are interested in digital-design are comparing it to the libraries listed below
- LatticeMico32 soft processor☆102Updated 10 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- CMod-S6 SoC☆37Updated 7 years ago
- Enigma in FPGA☆26Updated 5 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆58Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Project X-Ray Database: XC7 Series☆65Updated 3 years ago
- MR1 formally verified RISC-V CPU☆51Updated 6 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆60Updated last month
- Open PicoBlaze Assembler☆62Updated last year
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆34Updated 4 years ago
- FPGA USB 1.1 Low-Speed Implementation☆33Updated 6 years ago
- understanding the tinyfpga bootloader☆24Updated 6 years ago
- Virtual JTAG UART for Altera Devices☆45Updated 10 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆33Updated 4 years ago
- Repository and Wiki for Chip Hack events.☆50Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- Featherweight RISC-V implementation☆52Updated 3 years ago
- The OpenRISC 1000 architectural simulator☆72Updated 4 months ago
- Spen's Official OpenOCD Mirror☆48Updated 10 months ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 7 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆36Updated 4 years ago
- A Verilog Synthesis Regression Test☆35Updated 10 months ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆23Updated last year
- An Open Source configuration of the Arty platform☆124Updated last year
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆17Updated 2 months ago
- Export netlists from Yosys to DigitalJS☆47Updated last year
- Tools for FPGA development.☆44Updated last year