defano / digital-designLinks
An introduction to integrated circuit design with Verilog and the Papilio Pro development board.
☆14Updated 7 months ago
Alternatives and similar repositories for digital-design
Users that are interested in digital-design are comparing it to the libraries listed below
Sorting:
- LatticeMico32 soft processor☆106Updated 10 years ago
- An Open Source configuration of the Arty platform☆130Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆77Updated 2 years ago
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆148Updated 9 years ago
- Collection of open-source peripherals in Verilog☆179Updated 3 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆109Updated 6 years ago
- A utility for Composing FPGA designs from Peripherals☆182Updated 7 months ago
- Repository and Wiki for Chip Hack events.☆51Updated 4 years ago
- A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.☆203Updated 3 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆75Updated 2 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- ZPUino HDL implementation☆90Updated 7 years ago
- Simple UART controller for FPGA written in VHDL☆100Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- RISC-V CPU for OpenFPGAs, in Icestudio☆93Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 4 years ago
- A VHDL frontend for Yosys☆103Updated 8 years ago
- Documenting the Lattice ECP5 bit-stream format.☆56Updated 2 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- Open PicoBlaze Assembler☆63Updated last year
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- ARM4U☆35Updated 11 years ago
- Tools for FPGA development.☆48Updated this week
- Export netlists from Yosys to DigitalJS☆51Updated this week
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated 2 months ago
- Random ideas and interesting ideas for things we hope to eventually do.☆87Updated 3 years ago
- Generic Logic Interfacing Project☆46Updated 5 years ago