Alternatives and similar repositories for cs240lx-23spr

Users that are interested in cs240lx-23spr are comparing it to the libraries listed below

• Grubre / smol-gpu
  An rv32i inspired ISA, SIMT GPU implementation in system-verilog.
  ☆197Updated 5 months ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆81Updated last month
• johnwinans / rvalp
  RISC-V Assembly Language Programming
  ☆237Updated last year
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆111Updated 2 months ago
• stevehoover / LF-Building-a-RISC-V-CPU-Core
  ☆401Updated 5 months ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆243Updated 6 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆173Updated this week
• xmpf / awesome-risc-v
  Curated list of awesome resources related with RISC-V
  ☆88Updated 2 years ago
• fallingcat / HomebrewGPU
  HomebrewGPU is a simple ray tracing GPU on FPGA which implements basic ray-primitive intersection, BVH traversal, shadowing, reflection a…
  ☆207Updated 2 years ago
• rajesh-s / computer-architecture-and-systems-resources
  A curated list of Computer Architecture and Systems resources
  ☆543Updated 5 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆402Updated this week
• 0BAB1 / HOLY_CORE_COURSE
  Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with s…
  ☆198Updated last week
• agile-hw / labs
  Lab assignments for the Agile Hardware Design course
  ☆16Updated 2 months ago
• dddrrreee / cs240lx-22spr
  cs240lx class repo. except in very rare cases, cs140e is a hard requirement.
  ☆25Updated 2 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆148Updated 2 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• geohot / twitchcore
  It's a core. Made on Twitch.
  ☆261Updated 3 years ago
• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆207Updated 3 years ago
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆212Updated 5 months ago
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆50Updated 2 months ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆98Updated last week
• litex-hub / linux-on-litex-rocket
  Run 64-bit Linux on LiteX + RocketChip
  ☆201Updated last week
• sylefeb / tinygpus
  TinyGPUs, making graphics hardware for 1990s games
  ☆148Updated 4 months ago
• chipsalliance / t1
  ☆284Updated this week
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆181Updated 2 months ago
• toddmaustin / bringup-bench
  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …
  ☆183Updated 3 months ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆183Updated last week
• mikeroyal / RISC-V-Guide
  RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-…
  ☆593Updated last year
• riscv-software-src / riscv-unified-db
  Machine-readable database of the RISC-V specification, and tools to generate various views
  ☆98Updated this week
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆103Updated 2 months ago