Alternatives and similar repositories for RISC-V-Guide

Users that are interested in RISC-V-Guide are comparing it to the libraries listed below

• riscv / learn
  Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
  ☆934Updated 5 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,604Updated 3 weeks ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆642Updated 3 weeks ago
• stevehoover / LF-Building-a-RISC-V-CPU-Core
  ☆390Updated 3 months ago
• splinedrive / kianRiscV
  RISC-V Linux SoC, marchID: 0x2b
  ☆898Updated last week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆389Updated this week
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,792Updated this week
• riscv-non-isa / riscv-arch-test
  ☆567Updated last week
• riscv-software-src / opensbi
  RISC-V Open Source Supervisor Binary Interface
  ☆1,223Updated this week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆487Updated last month
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆357Updated 11 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆772Updated this week
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆639Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,041Updated 3 years ago
• Wren6991 / Hazard3
  3-stage RV32IMACZb* processor with debug
  ☆878Updated last week
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,038Updated 4 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆224Updated 5 months ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,808Updated 2 weeks ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,481Updated 3 years ago
• riscv / meta-riscv
  OpenEmbedded/Yocto layer for RISC-V Architecture
  ☆394Updated this week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆887Updated 4 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆274Updated 4 months ago
• riscv-non-isa / riscv-sbi-doc
  Documentation for the RISC-V Supervisor Binary Interface
  ☆414Updated last week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,084Updated this week
• riscv-software-src / riscv-tests
  ☆1,024Updated last week
• ESEO-Tech / emulsiV
  A visual simulator for teaching computer architecture using the RISC-V instruction set
  ☆287Updated 2 months ago
• riscv-collab / riscv-openocd
  Fork of OpenOCD that has RISC-V support
  ☆487Updated last week
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆223Updated 4 years ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆924Updated this week