geohot / twitchcoreLinks
It's a core. Made on Twitch.
☆263Updated 3 years ago
Alternatives and similar repositories for twitchcore
Users that are interested in twitchcore are comparing it to the libraries listed below
Sorting:
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,098Updated 5 months ago
- Enabling tinygrad compatibility with the Google Edge TPU☆79Updated last year
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,066Updated 9 months ago
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆222Updated last year
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆404Updated this week
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆702Updated 7 years ago
- VRoom! RISC-V CPU☆509Updated 11 months ago
- Open source machine learning accelerators☆386Updated last year
- 😎 A curated list of awesome RISC-V implementations☆138Updated 2 years ago
- Modular hardware build system☆1,066Updated this week
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆374Updated last year
- The OpenPiton Platform☆725Updated this week
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆304Updated 2 weeks ago
- ☆407Updated 5 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆174Updated last week
- Run 64-bit Linux on LiteX + RocketChip☆202Updated last month
- Basic RISC-V CPU implementation in VHDL.☆169Updated 4 years ago
- Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…☆518Updated 5 months ago
- ☆587Updated this week
- A Linux-capable RISC-V multicore for and by the world☆722Updated last week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆673Updated 3 weeks ago
- A simple RISC V core for teaching☆193Updated 3 years ago
- A minimal Tensor Processing Unit (TPU) inspired by Google's TPUv1.☆176Updated last year
- RISC-V Opcodes☆792Updated 3 weeks ago
- Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with s…☆216Updated 2 weeks ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆674Updated last month
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆240Updated 3 months ago
- RISC-V Assembly Language Programming☆239Updated last year
- Educational materials for RISC-V☆223Updated 4 years ago