Alternatives and similar repositories for twitchcore

Users that are interested in twitchcore are comparing it to the libraries listed below

• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,149Updated last month
• geohot / edgetpuxray
  Enabling tinygrad compatibility with the Google Edge TPU
  ☆85Updated last year
• UCSBarchlab / OpenTPU
  A open source reimplementation of Google's Tensor Processing Unit (TPU).
  ☆731Updated 8 years ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆223Updated last year
• google / CFU-Playground
  Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…
  ☆543Updated 10 months ago
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆516Updated last year
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆483Updated last week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,127Updated last week
• litex-hub / linux-on-litex-rocket
  Run 64-bit Linux on LiteX + RocketChip
  ☆209Updated 4 months ago
• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆1,249Updated last year
• eevaain / tiny-tpu-old
  A minimal Tensor Processing Unit (TPU) inspired by Google's TPUv1.
  ☆194Updated last year
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆376Updated 2 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆142Updated 2 years ago
• tensil-ai / tensil
  Open source machine learning accelerators
  ☆397Updated last year
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆172Updated 5 years ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆244Updated 8 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆229Updated 3 weeks ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆229Updated 2 years ago
• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆56Updated 3 weeks ago
• nickmqb / fpga_craft
  A voxel game/Minecraft clone for the iCE40 UP5K FPGA
  ☆208Updated 3 months ago
• openpower-cores / a2i
  ☆247Updated 3 years ago
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆313Updated this week
• splinedrive / kianRiscV
  RISC-V XV6/Linux SoC, marchID: 0x2b
  ☆1,060Updated last week
• litex-hub / fpga_101
  FPGA 101 lessons/labs
  ☆404Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆759Updated this week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆697Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆766Updated 4 months ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆331Updated 4 years ago
• johnwinans / rvalp
  RISC-V Assembly Language Programming
  ☆244Updated last month
• mosscomp / moss
  A computer for human beings.
  ☆49Updated last year