geohot / twitchcoreLinks
It's a core. Made on Twitch.
☆264Updated 3 years ago
Alternatives and similar repositories for twitchcore
Users that are interested in twitchcore are comparing it to the libraries listed below
Sorting:
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,114Updated last week
- Enabling tinygrad compatibility with the Google Edge TPU☆85Updated last year
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆222Updated last year
- Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…☆526Updated 7 months ago
- VRoom! RISC-V CPU☆511Updated last year
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,106Updated 11 months ago
- Run 64-bit Linux on LiteX + RocketChip☆202Updated 3 weeks ago
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆706Updated 7 years ago
- 😎 A curated list of awesome RISC-V implementations☆138Updated 2 years ago
- A minimal Tensor Processing Unit (TPU) inspired by Google's TPUv1.☆185Updated last year
- FPGA 101 lessons/labs☆394Updated last year
- RISC-V XV6/Linux SoC, marchID: 0x2b☆982Updated 2 weeks ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆430Updated last week
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆374Updated 2 years ago
- Modular hardware build system☆1,097Updated this week
- The OpenPiton Platform☆734Updated last month
- RISC-V Assembly Language Programming☆240Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆188Updated last week
- ☆448Updated 6 months ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆241Updated 5 months ago
- Marginally better than redstone☆100Updated 5 years ago
- A configurable RTL to bitstream FPGA toolchain☆48Updated this week
- Open source machine learning accelerators☆387Updated last year
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆679Updated 2 weeks ago
- Basic RISC-V CPU implementation in VHDL.☆169Updated 5 years ago
- Educational materials for RISC-V☆224Updated 4 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆327Updated 3 years ago
- ☆247Updated 3 years ago
- A voxel game/Minecraft clone for the iCE40 UP5K FPGA☆209Updated 4 years ago
- A Linux-capable RISC-V multicore for and by the world☆742Updated 3 weeks ago