cyyself / cpu232
The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully
☆9Updated 4 years ago
Alternatives and similar repositories for cpu232
Users that are interested in cpu232 are comparing it to the libraries listed below
Sorting:
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- SoC for CQU Dual Issue Machine☆12Updated 2 years ago
- The 'missing header' for Chisel☆20Updated last month
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- CQU Dual Issue Machine☆36Updated 10 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆41Updated 9 months ago
- Run Rocket Chip on VCU128☆30Updated 5 months ago
- nscscc2018☆26Updated 6 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆21Updated 2 months ago
- Documentation for Digital Design course☆20Updated 2 months ago
- Lower chisel memories to SRAM macros☆12Updated last year
- riscv32i-cpu☆18Updated 4 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆11Updated last year
- A Rocket-Chip with a Dynamically Randomized LLC☆13Updated 7 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- ☆15Updated 2 months ago
- BOOM's Simulation Accelerator.☆14Updated 3 years ago
- USTC 并行程序设计实验☆8Updated 3 years ago
- ☆14Updated last month
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆31Updated last year
- What if everything is a io_uring?☆16Updated 2 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆15Updated 6 months ago
- 第六届龙芯杯混元形意太极门战队作品☆17Updated 3 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆16Updated last week
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 5 years ago
- Running ahead of memory latency - Part II project☆10Updated 2 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago