Alternatives and similar repositories for llvm-cjg:

Users that are interested in llvm-cjg are comparing it to the libraries listed below

• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆42Updated 7 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆97Updated 3 years ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆110Updated last month
• srokicki / HybridDBT
  ☆32Updated 4 years ago
• frasercrmck / llvm-leg
  ☆107Updated 3 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆98Updated 2 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆93Updated last week
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• andreaskuster / black-parrot-branch-predictor
  Branch Predictor Optimization for BlackParrot
  ☆15Updated last year
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆75Updated last year
• riscv / riscv-CMOs
  ☆86Updated 2 years ago
• riscvarchive / riscv-code-size-reduction
  ☆150Updated last year
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 3 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆151Updated 2 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆114Updated 4 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆190Updated 9 months ago
• riscv / riscv-test-env
  ☆46Updated 3 weeks ago
• leros-dev / leros
  A Tiny Processor Core
  ☆107Updated last month
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆83Updated last year
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆149Updated this week
• ARM-software / tarmac-trace-utilities
  Tools for analyzing and browsing Tarmac instruction traces.
  ☆75Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆225Updated 5 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆91Updated 3 weeks ago
• UCTECHIP / rocket_chip_vpu
  ☆10Updated 4 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 8 months ago
• ISRC-CAS / c910-llvm
  平头哥玄铁C910的LLVM工具链支持，由PLCT实验室提供，非官方版本
  ☆68Updated 4 years ago