cjdrake / pyedaLinks
Python EDA
☆341Updated last year
Alternatives and similar repositories for pyeda
Users that are interested in pyeda are comparing it to the libraries listed below
Sorting:
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆293Updated 2 months ago
- A circuit toolkit☆107Updated 5 years ago
- Showcase examples for EPFL logic synthesis libraries☆202Updated last year
- magma circuits☆264Updated last year
- HW Design: A Functional Approach☆145Updated 2 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆444Updated 5 months ago
- Tools for working with circuits as graphs in python☆126Updated 2 years ago
- CUDD Decision Diagram Package☆151Updated last month
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆133Updated 6 years ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- C++ logic network library☆274Updated 4 months ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆231Updated last week
- A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.☆168Updated 5 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Updated last month
- Python-based hardware modeling framework☆245Updated 6 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆47Updated last year
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆324Updated last year
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆313Updated 7 months ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- AIGER And-Inverter-Graph Library☆97Updated 3 weeks ago
- ☆114Updated 4 years ago
- ☆104Updated 3 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆487Updated this week
- An advanced header-only exact synthesis library☆30Updated 3 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆120Updated 8 months ago
- ASTRAN - Automatic Synthesis of Transistor Networks☆66Updated 3 years ago
- EPFL logic synthesis benchmarks☆226Updated 2 months ago
- A Modeling and Verification Platform for SoCs using ILAs☆81Updated last year
- A logic synthesis tool☆85Updated 4 months ago
- Python wrapper for verilator model☆92Updated last year