Python EDA
☆344Dec 30, 2024Updated last year
Alternatives and similar repositories for pyeda
Users that are interested in pyeda are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Boolean Expressions☆21Nov 5, 2018Updated 7 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,228Updated this week
- Binary Decision Diagrams (BDDs) in pure Python and Cython wrappers of CUDD, Sylvan, and BuDDy☆220Dec 11, 2025Updated 9 months ago
- A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.☆175Apr 11, 2020Updated 6 years ago
- CUDD Decision Diagram Package☆169Dec 12, 2025Updated 9 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Tools for working with circuits as graphs in python☆131Nov 17, 2023Updated 2 years ago
- IPython Magic Functions☆16Aug 14, 2017Updated 9 years ago
- GuidedSampler: Coverage-guided Sampling of SMT Solutions☆15Jul 9, 2025Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆46Jul 17, 2024Updated 2 years ago
- An abstraction library for interfacing EDA tools☆797Sep 15, 2026Updated last week
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 3 years ago
- Showcase examples for EPFL logic synthesis libraries☆210Apr 5, 2024Updated 2 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- GPU-based logic synthesis tool☆111Mar 31, 2026Updated 5 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆25Jun 23, 2024Updated 2 years ago
- "High density" digital standard cells for SKY130 provided by SkyWater.☆28Feb 22, 2023Updated 3 years ago
- Logic Minimization in Python☆26Mar 25, 2026Updated 6 months ago
- A toolkit for SAT-based prototyping in Python☆461Aug 16, 2026Updated last month
- C++ logic network library☆310Updated this week
- IDEA project source files☆115Apr 15, 2026Updated 5 months ago
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆16Feb 22, 2026Updated 7 months ago
- Logic circuit analysis and optimization☆52Feb 2, 2026Updated 7 months ago
- A logic synthesis tool☆90Aug 8, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆327Mar 8, 2026Updated 6 months ago
- OpenSTA engine☆622Updated this week
- A simple Python Binary Decision Diagram (BDD) that outputs .dot files. It can also create minimal BDDs. Should be used mostly for educati…☆14Jan 8, 2014Updated 12 years ago
- Awesome machine learning for logic synthesis☆30Sep 21, 2022Updated 4 years ago
- Specify and synthesize systems using symbolic algorithms☆53Dec 15, 2025Updated 9 months ago
- A tool for analysing the source-level static connectivity of a SystemVerilog design☆29Updated this week
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 9 years ago
- Cross EDA Abstraction and Automation☆43Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,271Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆802Jun 15, 2024Updated 2 years ago
- ☆21Oct 27, 2022Updated 3 years ago
- SystemVerilog synthesis tool☆237Mar 10, 2025Updated last year
- STRIPS benchmarks for classical planning☆16Mar 29, 2022Updated 4 years ago
- Netlist API (and more) for EDA flow development☆163Updated this week
- The first large scale formally verified reasoning dataset for Verilog☆25May 16, 2025Updated last year
- Rsyn – An Extensible Physical Synthesis Framework☆143Jul 20, 2024Updated 2 years ago