Python EDA
☆344Dec 30, 2024Updated last year
Alternatives and similar repositories for pyeda
Users that are interested in pyeda are comparing it to the libraries listed below
Sorting:
- Boolean Expressions☆21Nov 5, 2018Updated 7 years ago
- Binary Decision Diagrams (BDDs) in pure Python and Cython wrappers of CUDD, Sylvan, and BuDDy☆216Dec 11, 2025Updated 2 months ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,129Feb 27, 2026Updated last week
- GuidedSampler: Coverage-guided Sampling of SMT Solutions☆15Jul 9, 2025Updated 8 months ago
- IPython Magic Functions☆16Aug 14, 2017Updated 8 years ago
- A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.☆168Apr 11, 2020Updated 5 years ago
- CUDD Decision Diagram Package☆155Dec 12, 2025Updated 2 months ago
- Tools for working with circuits as graphs in python☆126Nov 17, 2023Updated 2 years ago
- An abstraction library for interfacing EDA tools☆756Feb 18, 2026Updated 2 weeks ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Jul 17, 2024Updated last year
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Showcase examples for EPFL logic synthesis libraries☆202Apr 5, 2024Updated last year
- Logic Minimization in Python☆26Feb 23, 2026Updated 2 weeks ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 2 years ago
- Specify and synthesize systems using symbolic algorithms☆52Dec 15, 2025Updated 2 months ago
- ☆23Jun 23, 2024Updated last year
- IDEA project source files☆112Oct 15, 2025Updated 4 months ago
- C++ logic network library☆280Sep 30, 2025Updated 5 months ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 9 months ago
- Code for the NeurIPS 2020 paper Efficient Exact Verification of Binarized Neural Networks☆13Jun 30, 2022Updated 3 years ago
- Logic circuit analysis and optimization☆45Feb 2, 2026Updated last month
- GPU-based logic synthesis tool☆100Nov 27, 2025Updated 3 months ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,210Updated this week
- OpenSTA engine☆551Updated this week
- A SAT solver implementation in VHDL, team tussle☆21Apr 13, 2016Updated 9 years ago
- A logic synthesis tool☆84Sep 8, 2025Updated 6 months ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆135Updated this week
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆325Aug 10, 2024Updated last year
- "High density" digital standard cells for SKY130 provided by SkyWater.☆23Feb 22, 2023Updated 3 years ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 11 years ago
- A copy of the latest version of MVSIS☆12Apr 18, 2021Updated 4 years ago
- MiniCard: An efficient cardinality solver based on MiniSAT☆19Jun 22, 2025Updated 8 months ago
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆15Feb 22, 2026Updated 2 weeks ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- A toolkit for SAT-based prototyping in Python☆446Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆774Jun 15, 2024Updated last year
- design and verification of asynchronous circuits☆43Feb 27, 2026Updated last week
- Rsyn – An Extensible Physical Synthesis Framework☆137Jul 20, 2024Updated last year