Alternatives and similar repositories for mil1553-spi:

Users that are interested in mil1553-spi are comparing it to the libraries listed below

• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆25Updated 5 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated 2 months ago
• johnathan-convertino-afrl / open1553
  Projects for building MIL-STD-1553 communications devices
  ☆24Updated 7 months ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆21Updated 7 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• bggardner / can-lite-vhdl
  A lightweight Controller Area Network (CAN) controller in VHDL
  ☆26Updated 5 months ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆17Updated 4 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆43Updated 3 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated last month
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆51Updated this week
• suoto / fpga_cores
  ☆33Updated last year
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• rprinz08 / arty-s7-multinic
  ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface
  ☆13Updated 4 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆45Updated 4 years ago
• BerkeleyLab / Marble-Mini
  "Marble-Mini" Simple FMC carrier board with SFP, 2x FMC, PoE
  ☆18Updated 3 years ago
• olofk / observer
  ☆41Updated 4 years ago
• hamsternz / ArtyEtherentTX
  Sending raw data from the Digilent Arty FPGA board
  ☆23Updated 8 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 2 weeks ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆55Updated last week
• DiegoRosales / VHDL_Modules
  VHDL Modules
  ☆24Updated 10 years ago
• jevinskie / aes-over-pcie
  A VHDL implementation of 128 bit AES encryption with a PCIe interface.
  ☆26Updated 8 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆67Updated 7 years ago
• xupsh / Amp-zynq
  Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors
  ☆20Updated 9 years ago
• linuxbest / ahci_mpi
  an sata controller using smallest resource.
  ☆15Updated 11 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆36Updated 2 years ago