Alternatives and similar repositories for RISC-CPU

Users that are interested in RISC-CPU are comparing it to the libraries listed below

• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆26Updated 8 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• openhwgroup / core-v-sw
  Main Repo for the OpenHW Group Software Task Group
  ☆17Updated 10 months ago
• pulp-platform / pulp-freertos
  FreeRTOS for PULP
  ☆16Updated 2 years ago
• intel / fpga-runtime-for-opencl
  Intel® FPGA Runtime for OpenCL™ Software Technology
  ☆35Updated 11 months ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆64Updated last year
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆20Updated 7 years ago
• RohanNagar / parallel-logic-networks
  Gate-Level Simulation on a GPU
  ☆10Updated 9 years ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆50Updated last year
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated 2 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆50Updated this week
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆16Updated last year
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆91Updated 6 years ago
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆15Updated 10 months ago
• riscv-non-isa / riscv-semihosting
  ☆32Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆95Updated last year
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• ROCm / hipSPARSELt
  [DEPRECATED] Moved to ROCm/rocm-libraries repo
  ☆12Updated 2 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated this week
• ROCm / hipRAND
  [DEPRECATED] Moved to ROCm/rocm-libraries repo
  ☆26Updated 2 weeks ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated 2 weeks ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• Fedex100 / awesome-compilers
  ☆18Updated 8 years ago
• synogate / gatery
  Gatery, a library for circuit design.
  ☆22Updated last year
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆18Updated 9 months ago
• leos313 / DOOM_FPGA
  Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
  ☆20Updated 5 years ago
• intel / tiny-tensor-compiler
  ☆21Updated 2 weeks ago
• antmicro / verilator-old-archived
  ☆21Updated 2 years ago
• fmozafari / angel
  C++ Library for Quantum State Preparation (QSP)
  ☆12Updated 3 years ago