alirezakay / RISC-CPULinks
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
☆29Updated 4 years ago
Alternatives and similar repositories for RISC-CPU
Users that are interested in RISC-CPU are comparing it to the libraries listed below
Sorting:
- FreeRTOS for PULP☆13Updated 2 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Intel® FPGA Runtime for OpenCL™ Software Technology☆34Updated 7 months ago
- This repository contains sample code integrating Renode with Verilator☆22Updated 3 months ago
- Main Repo for the OpenHW Group Software Task Group☆17Updated 6 months ago
- ☆19Updated last week
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆14Updated 6 months ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- ☆32Updated last week
- Documentation of the RISC-V C API☆77Updated last week
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆62Updated 9 months ago
- C++17 implementation of an AST for Verilog code generation☆25Updated 2 years ago
- CV32E40X Design-Verification environment☆13Updated last year
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆14Updated last month
- Convert C files into Verilog☆19Updated 6 years ago
- [DEPRECATED] Moved to ROCm/rocm-libraries repo☆26Updated last week
- User-Mode Driver for Tenstorrent hardware☆33Updated this week
- An awesome curated list of languages and tools to program FPGAs☆65Updated 3 years ago
- Simple runtime for Pulp platforms☆49Updated last month
- Curated list of awesome resources related with RISC-V☆88Updated 3 years ago
- Gate-Level Simulation on a GPU☆10Updated 8 years ago
- ☆24Updated this week
- [DEPRECATED] Moved to ROCm/rocm-libraries repo☆12Updated this week
- Example for running IREE in a bare-metal Arm environment.☆40Updated last month
- The PE for the second generation CGRA (garnet).☆17Updated 5 months ago
- The multi-core cluster of a PULP system.☆108Updated last week
- 🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…☆19Updated this week
- FPGA Assembly (FASM) Parser and Generator☆97Updated 3 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆37Updated 6 months ago
- A powerful and modern open-source architecture description language.☆42Updated 7 years ago