Alternatives and similar repositories for RISC-CPU:

Users that are interested in RISC-CPU are comparing it to the libraries listed below

• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆42Updated 2 weeks ago
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 9 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆80Updated this week
• VP-Vibes / VPV-Peripherals
  Library of example SystemC/TLM peripherals for various SoCs based on the SCS library
  ☆12Updated last week
• shehanmunasinghe / tinyGPU
  tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
  ☆43Updated 3 years ago
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆21Updated 3 years ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆28Updated last year
• pulp-platform / hero-sdk
  ⛔ DEPRECATED ⛔ HERO Software Development Kit
  ☆20Updated 3 years ago
• intel / fpga-runtime-for-opencl
  Intel® FPGA Runtime for OpenCL™ Software Technology
  ☆33Updated 2 weeks ago
• sdasgup3 / parallel-processor-design
  Super scalar Processor design
  ☆21Updated 10 years ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆19Updated last month
• nvdla / simple_cpu
  NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)
  ☆18Updated 6 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆47Updated last month
• intel / FPGA-Devcloud
  Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically f…
  ☆119Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆139Updated 2 weeks ago
• fpgaemu / fpgaemu
  Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos Schoo…
  ☆45Updated 2 years ago
• riscv-software-src / riscv-isac
  ☆32Updated 4 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆75Updated 3 months ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆86Updated 5 years ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆16Updated 6 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆43Updated 3 months ago
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆143Updated last week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated this week
• riscvarchive / riscv-zicond
  The ISA specification for the ZiCondOps extension.
  ☆19Updated 11 months ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆47Updated 6 months ago
• pulp-platform / redmule
  ☆47Updated this week
• pulp-platform / gvsoc
  Pulp virtual platform
  ☆23Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆85Updated 3 weeks ago