Quickstart guide on Icarus Verilog.
☆41Jun 18, 2020Updated 5 years ago
Alternatives and similar repositories for iverilog-tutorial
Users that are interested in iverilog-tutorial are comparing it to the libraries listed below
Sorting:
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 9 years ago
- ☆14Oct 11, 2024Updated last year
- A continuous local search SAT solver based on Fourier expansion for hybrid Boolean constraints.☆12Sep 18, 2024Updated last year
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated 11 months ago
- ☆10Oct 15, 2021Updated 4 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- propositional satisfiability problem (SAT) goes neural and deep☆12Aug 17, 2021Updated 4 years ago
- Official repository for paper "Goal-Aware Neural SAT Solver"☆17Jun 10, 2023Updated 2 years ago
- Official Repository for the ICLR 2022 paper "Generalization of Neural Combinatorial Solvers through the Lens of Adversarial Robustness"☆13Nov 20, 2022Updated 3 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 9 months ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆20Jul 12, 2023Updated 2 years ago
- SystemVerilog FSM generator☆35May 5, 2024Updated last year
- An LLVM based mini-C to Verilog High-level Synthesis tool☆39Mar 7, 2025Updated 11 months ago
- ☆15Nov 9, 2022Updated 3 years ago
- Hardware Formal Verification☆17Aug 10, 2020Updated 5 years ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- A Formal Verification Framework for Chisel☆19Apr 9, 2024Updated last year
- ☆16Dec 30, 2023Updated 2 years ago
- ☆72Feb 14, 2023Updated 3 years ago
- A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.☆16Apr 25, 2024Updated last year
- High quality and composable RTL libraries in SystemVerilog☆31Updated this week
- Benchmarks for Approximate Circuit Synthesis☆17Aug 2, 2020Updated 5 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- ☆23Mar 13, 2023Updated 2 years ago
- ☆19Jul 12, 2024Updated last year
- [NeurIPS 2022] "NSNet: A General Neural Probabilistic Framework for Satisfiability Problems"☆19Mar 29, 2023Updated 2 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- Stereo digital 2-way crossover filters processing I2S audio (16bit or 24bit) streams☆22May 13, 2024Updated last year
- An Extensible Framework for Hardware Verification and Debugging☆18Sep 14, 2022Updated 3 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Mar 7, 2019Updated 6 years ago
- ☆21Jan 25, 2018Updated 8 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- MachSMT: An ML-Driven Algorithm Selection tool for SMT Solvers☆25Apr 21, 2023Updated 2 years ago
- Graph your gate-level verilog code as a directed graph!☆18Nov 3, 2020Updated 5 years ago
- A Python API for the MiniSat and MiniCard constraint solvers.☆22Jan 1, 2026Updated 2 months ago
- Integer Multiplier Generator for Verilog☆24Jul 4, 2025Updated 8 months ago
- ☆20Jul 7, 2017Updated 8 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Dec 23, 2025Updated 2 months ago