☆25Aug 9, 2026Updated 3 months ago
Alternatives and similar repositories for power-estimation-VCD-SKY130
Users that are interested in power-estimation-VCD-SKY130 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆55Jul 11, 2025Updated last year
- Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.☆129Updated this week
- A PCIe RTL implementation☆27Aug 16, 2026Updated 2 months ago
- Open source synthesizable MJPEG encoder written in behavioral RTL with AXI interfaces, up to 1080p30 on low end AMD/Xilinx 7-Series FPGAs☆17Oct 10, 2026Updated last month
- A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers☆10Jan 2, 2026Updated 10 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- ElemRV - End-to-end Open-Source RISC-V Microcontroller☆151Updated this week
- An analog circuit topology benchmark for LLMs☆17Jun 23, 2026Updated 4 months ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 8 months ago
- The UVM written in Python☆18Updated this week
- Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.☆42Jul 30, 2026Updated 3 months ago
- Tiny tool for scraping essential data needed for generating BOM☆10Apr 29, 2021Updated 5 years ago
- nvc + xsim = encrypted IP and, quite possibly, eternal glory☆26Updated this week
- high level VHDL floating point library for synthesis in fpga☆18Oct 29, 2026Updated 2 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Generates a SystemVerilog assertion interface for a given SV RTL design☆20Mar 23, 2025Updated last year
- NEORV32 RISC-V SoC running Zephyr RTOS on FPGA bare metal - with an extensible accelerator pipeline architecture, including an DMA-enable…☆18Aug 16, 2026Updated 2 months ago
- 📸 ADCs for faster image sensors☆13Updated this week
- RISC-V SoC — Complete RTL-to-GDSII Flow (SKY130 130nm) | 34 Hardened Modules | 107K+ Gates☆27May 17, 2026Updated 5 months ago
- A fast, open-source DRC (Design Rule Check) engine for GDSII layouts.☆63Updated this week
- A minimal neuromorphic chip design in SystemVerilog to learn how brain-inspired computing works from the ground up.☆29Mar 30, 2026Updated 7 months ago
- openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and…☆28Updated this week
- Simple UVM environment for experimenting with Verilator.☆54Sep 9, 2026Updated 2 months ago
- Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)☆36Jul 24, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Embedded Box, containerized development environments for embedded and FPGA designers☆22Jul 4, 2026Updated 4 months ago
- VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration☆66Updated this week
- Analog HDL Design Full-stack Agents☆25Jun 8, 2026Updated 5 months ago
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆29Aug 12, 2026Updated 3 months ago
- Open source ISS and logic RISC-V 32 bit project☆62Sep 1, 2026Updated 2 months ago
- Data Science Foundations: Python Scientific Stack☆11Jun 2, 2022Updated 4 years ago
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆20Apr 6, 2022Updated 4 years ago
- CVA6 softcore contest☆27Nov 5, 2026Updated last week
- RTL Interview Questions☆12Mar 23, 2019Updated 7 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively☆46Oct 28, 2026Updated 2 weeks ago
- ideas and eda software for vlsi design☆51Nov 3, 2026Updated last week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆112Aug 31, 2026Updated 2 months ago
- A curated list of AI accelerator papers, resources, tools, and open-source projects.☆184Jul 12, 2026Updated 4 months ago
- A tapeout-ready structure for hierarchical analog design (v0.1).☆26Jan 16, 2026Updated 9 months ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- have you joined the skule webring? you should join the skule webring.☆15Aug 4, 2026Updated 3 months ago
Are these results useful?