Alternatives and similar repositories for rules_vivado

Users that are interested in rules_vivado are comparing it to the libraries listed below

• hdl / bazel_rules_hdl
  Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…
  ☆151Updated last month
• Lightelligence / rules_verilog
  Bazel build rules for compiling Verilog
  ☆21Updated last year
• kkiningh / rules_verilator
  Bazel build rules for Verilator
  ☆24Updated last year
• bazelembedded / bazel-embedded
  Tools for embedded/bare-metal development using bazel
  ☆112Updated last year
• hzeller / bant
  Bazel/Build Analysis and Navigation Tool
  ☆27Updated 2 weeks ago
• antmicro / coverview
  Coverview
  ☆25Updated 3 weeks ago
• bavovanachte / sphinx-wavedrom
  A sphinx extension that allows including wavedrom diagrams by using its text-based representation
  ☆38Updated last year
• antmicro / zynq-mkbootimage
  An open source replacement of the Xilinx bootgen application.
  ☆113Updated last year
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆116Updated last year
• hexdae / toolchains_arm_gnu
  ARM embedded toolchains for Bazel
  ☆141Updated last month
• antmicro / warp-pipe
  ☆16Updated last year
• z4yx / petalinux-docker
  Dockerfile to build docker images with Petalinux (Tested on version 2018.3~2021.1)
  ☆121Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• kevinpt / symbolator
  HDL symbol generator
  ☆200Updated 2 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆60Updated last month
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆242Updated 4 months ago
• jhallen / vivado_setup
  How to set up Xilinx Vivado for source control
  ☆108Updated last year
• rickwebiii / bazel_fpga_rules
  Rules for performing tasks related to FPGA development in Bazel.
  ☆12Updated 4 years ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆284Updated 6 years ago
• edaa-org / pyEDAA.IPXACT
  An IP-XACT DOM for IEEE 1685-2014 in Python.
  ☆31Updated last month
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆81Updated 3 years ago
• pieter3d / simview
  ☆88Updated 2 months ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆341Updated this week
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 4 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆252Updated last year
• filmil / vivado-docker
  Docker installation of Vivado tooling
  ☆32Updated 4 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆108Updated 7 years ago
• yne / vcd
  VCD file (Value Change Dump) command line viewer
  ☆120Updated 2 months ago
• Xilinx / yocto-manifests
  Repo Manifests for the Yocto Project Build System
  ☆39Updated last month