Alternatives and similar repositories for vscode

Users that are interested in vscode are comparing it to the libraries listed below

• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆71Updated this week
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated last year
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 2 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆53Updated 4 years ago
• darklife / udarkrisc
  u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
  ☆15Updated last year
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆44Updated 2 years ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆41Updated last month
• openXC7 / openXC7-snap
  snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support
  ☆28Updated 10 months ago
• Mecrisp / Nandland-RISC-V
  RISC-V Playground on Nandland Go
  ☆16Updated 2 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 3 weeks ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆47Updated this week
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated last month
• sellicott / tcc-riscv32
  Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…
  ☆69Updated this week
• MichaelBell / nanoV
  RISC-V RV32E core designed for minimal area
  ☆16Updated 6 months ago
• fallen / SucreLA
  Open source Logic Analyzer based on LiteX SoC
  ☆25Updated last month
• AntonMause / rv16poc
  16 bit RISC-V proof of concept
  ☆24Updated 8 months ago
• olofk / qerv
  ☆16Updated 3 weeks ago
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆24Updated 2 years ago
• Chalandi / Blinky_Pico2_dual_core_nosdk
  Bare-metal programming on RP2350 dual-core ARM Cortex-m33/RISC-V Hazard3 (non-SDK)
  ☆14Updated 2 weeks ago
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆16Updated 2 years ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆40Updated 2 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆37Updated 4 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated last month
• gatecat / tinytapeout-fpga-test
  ☆13Updated 2 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 3 years ago
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆35Updated last year
• amaranth-lang / rfcs
  RFCs for changes to the Amaranth language and standard components
  ☆18Updated 3 weeks ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 4 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆43Updated 3 months ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆38Updated 6 months ago