Yinxiao-Feng / chiplet-actuaryLinks
Cost Model
☆14Updated 3 months ago
Alternatives and similar repositories for chiplet-actuary
Users that are interested in chiplet-actuary are comparing it to the libraries listed below
Sorting:
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆205Updated 2 years ago
- NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)☆116Updated 6 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆240Updated 2 years ago
- ☆34Updated last month
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆189Updated 4 years ago
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆170Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆26Updated 2 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆133Updated last month
- BookSim 2.0☆344Updated last year
- Repository to host and maintain scale-sim-v2 code☆315Updated 2 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- A list of our chiplet simulaters☆33Updated 3 weeks ago
- Processing-In-Memory (PIM) Simulator☆174Updated 7 months ago
- RTL implementation of Flex-DPE.☆106Updated 5 years ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆218Updated last year
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆473Updated last year
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆16Updated last year
- An Open-Source Tool for CGRA Accelerators☆67Updated 3 months ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆380Updated 11 months ago
- ☆24Updated 3 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 4 months ago
- gem5 repository to study chiplet-based systems☆76Updated 6 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆84Updated 2 months ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- A pre-RTL, power-performance model for fixed-function accelerators☆177Updated last year
- An integrated CGRA design framework☆90Updated 3 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆147Updated this week
- ☆77Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month