Standalone Access Registration (SAR) is the process by which a device registers with a 5G network to gain access to its services. It involves various registration procedures, messages, and security measures to ensure authorized access and mutual authentication.
☆24Mar 25, 2023Updated 3 years ago
Alternatives and similar repositories for 5g-nr-standalone
Users that are interested in 5g-nr-standalone are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- Library to decode/encode ASN.1 protocol (PER only)☆13Dec 29, 2023Updated 2 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆13Mar 16, 2018Updated 8 years ago
- VHDL related news.☆27Updated this week
- LiteX Accelerator Block for GNU Radio☆23Feb 6, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RFSoC2x2 board repo for PYNQ☆17Oct 11, 2022Updated 3 years ago
- 5G NR-ARFCN calculator, as a Python package☆18Apr 16, 2026Updated 4 months ago
- Rasdisys Open Source code for a LTE eNB on Qualcomm FSM9955☆43Jun 1, 2021Updated 5 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- Qfsm is a graphical tool for designing finite state machine, written in C++ using the Qt library☆11Nov 19, 2018Updated 7 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆33Sep 1, 2022Updated 3 years ago
- Implemented a prototype of gNB-CU-UP a network element of 5G Radio Network. Using DPDK, a set of data-plane processing libraries and NIC …☆19Nov 27, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Private 5G Book☆80Nov 27, 2025Updated 8 months ago
- 5G K-SimNet (5G Network Simulator)☆22Jul 19, 2019Updated 7 years ago
- VCD Parser for Node.js☆11Jan 7, 2023Updated 3 years ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 3 years ago
- 3G/4G/5G authentication test troubleshooting tool☆62May 11, 2020Updated 6 years ago
- A series of simulations organized as homework assignments that were part of the course on Neuromorphic Engineering at IIT Bombay (course …☆10Jul 19, 2016Updated 10 years ago
- MATLAB-based testing tools for the srsRAN Project https://github.com/srsran/srsRAN_Project☆43Mar 27, 2026Updated 4 months ago
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- Rust compile-time type information experiment☆19Jan 24, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Nanoscale logging library in C++11☆14Dec 15, 2021Updated 4 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆19Dec 5, 2022Updated 3 years ago
- A simple Emacs minor mode for VUnit☆12Jul 14, 2025Updated last year
- This app create virtual gateway for multiple networks with same subnet☆19Aug 7, 2022Updated 4 years ago
- Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction☆12Apr 21, 2022Updated 4 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- LLMShark: Comprehensive analysis tool for LLM streaming traffic from PCAP files☆20Jun 12, 2025Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- the trilateration software for the Distributed Ground Station Network☆10Jan 12, 2021Updated 5 years ago
- A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog☆233Apr 29, 2025Updated last year
- Dockerfile with Vivado for CI☆12Apr 27, 2025Updated last year
- An online Verilog IDE based on YosysJS.☆25Jan 7, 2016Updated 10 years ago
- Binary Optimization and Layout Tool - A linux command-line utility used for optimizing performance of binaries☆12Jul 7, 2020Updated 6 years ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 4 years ago
- This repository describes two frameworks which can be used for pre-Silicon power side-channel analysis of digital circuit designs (i.e., …☆16Feb 16, 2022Updated 4 years ago