Standalone Access Registration (SAR) is the process by which a device registers with a 5G network to gain access to its services. It involves various registration procedures, messages, and security measures to ensure authorized access and mutual authentication.
☆24Mar 25, 2023Updated 3 years ago
Alternatives and similar repositories for 5g-nr-standalone
Users that are interested in 5g-nr-standalone are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- free5GC 5GC & srsRAN 5G with ZeroMQ UE / RAN Sample Configuration☆14May 16, 2026Updated last month
- Library to decode/encode ASN.1 protocol (PER only)☆13Dec 29, 2023Updated 2 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Mar 16, 2018Updated 8 years ago
- Python scripts for converting trace log messages to sequence diagrams. Visually debug trace logs.☆36Jan 11, 2023Updated 3 years ago
- The ASN.1 Compiler☆14Jul 10, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Digital IC design and vlsi notes☆14Jun 24, 2020Updated 5 years ago
- ☆25Mar 30, 2016Updated 10 years ago
- Scripts for the "ITU-ML5G-PS-006: ML5G-PHY-Reinforcement learning: scheduling and resource allocation"☆31Sep 22, 2021Updated 4 years ago
- TSQP: Safeguarding Real-Time Inference for Quantization Neural Networks on Edge Devices (Accepted to S&P 2025)☆17Sep 16, 2025Updated 9 months ago
- LiteX Accelerator Block for GNU Radio☆24Feb 6, 2022Updated 4 years ago
- VHDL grammar for tree-sitter☆32Dec 20, 2023Updated 2 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- 5G NR-ARFCN calculator, as a Python package☆17Apr 16, 2026Updated 2 months ago
- SystemVerilog FSM generator☆39May 10, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Qfsm is a graphical tool for designing finite state machine, written in C++ using the Qt library☆11Nov 19, 2018Updated 7 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- Implemented a prototype of gNB-CU-UP a network element of 5G Radio Network. Using DPDK, a set of data-plane processing libraries and NIC …☆18Nov 27, 2021Updated 4 years ago
- Private 5G Book☆78Nov 27, 2025Updated 6 months ago
- 3G/4G/5G authentication test troubleshooting tool☆62May 11, 2020Updated 6 years ago
- A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog☆231Apr 29, 2025Updated last year
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- 5G K-SimNet (5G Network Simulator)☆22Jul 19, 2019Updated 6 years ago
- Nanoscale logging library in C++11☆14Dec 15, 2021Updated 4 years ago
- A simple Emacs minor mode for VUnit☆12Jul 14, 2025Updated 11 months ago
- Hardware CD/CI and Development Containers 🚢☆11Jul 20, 2022Updated 3 years ago
- Unofficial nextpnr WebAssembly packages☆17Mar 11, 2026Updated 3 months ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- EC499: Major Project☆11Jun 25, 2023Updated 2 years ago
- Test program for AF_PACKET☆12Apr 21, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- ☆21Nov 23, 2022Updated 3 years ago
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆38Oct 19, 2020Updated 5 years ago
- ioctl helper functions☆13Mar 26, 2018Updated 8 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- SRAM macros created for the GF180MCU provided by GlobalFoundries.☆20Apr 10, 2023Updated 3 years ago
- Dockerfile with Vivado for CI☆12Apr 27, 2025Updated last year