Alternatives and similar repositories for BitstreamEvolution

Users that are interested in BitstreamEvolution are comparing it to the libraries listed below

• HLSTransform / submission
  ☆119Updated 2 years ago
• chipsalliance / silicon-notebooks
  ☆173Updated 2 years ago
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆157Updated this week
• kaushalmodi / nim-systemverilog-dpic
  Using Nim to interface with SystemVerilog test benches via DPI-C
  ☆31Updated 8 months ago
• librelane / librelane
  ASIC implementation flow infrastructure, successor to OpenLane
  ☆276Updated this week
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆104Updated 3 weeks ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆126Updated 2 years ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆123Updated last week
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆94Updated last year
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆48Updated 3 weeks ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆81Updated last month
• kiwih / qtcore-C1
  ☆47Updated 2 years ago
• efabless / chipignite-resources
  ☆86Updated 3 years ago
• apytypes / apytypes
  APyTypes - Algorithmic data types for Python
  ☆39Updated last week
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆128Updated 3 years ago
• phanrahan / magma
  magma circuits
  ☆264Updated last year
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆255Updated 4 months ago
• asyncvlsi / actflow
  Top-level repository for the ACT EDA flow
  ☆37Updated last week
• Kuree / kratos
  Debuggable hardware generator
  ☆71Updated 2 years ago
• bsc-loca / sargantana
  ☆126Updated 5 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆215Updated last week
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆131Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆164Updated 2 months ago
• UCSBarchlab / PyRTL
  A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…
  ☆293Updated 2 months ago
• NVlabs / AutoDMP
  ☆157Updated 2 years ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆95Updated last year
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆445Updated 5 months ago
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆202Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated 3 weeks ago