UofT-HPRC / fake_fpga

Related projects ⓘ

Alternatives and complementary repositories for fake_fpga

• sifferman / fusesoc_template
  Example of how to get started with olofk/fusesoc.
  ☆15Updated 3 years ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆45Updated last month
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• tms4517 / 2D-Systolic-Array-Multiplier
  2D Systolic Array Multiplier
  ☆11Updated 9 months ago
• WajahatRiaz / QuadSPI
  RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.
  ☆18Updated 2 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆17Updated 5 months ago
• ATaylorCEngFIET / introduction_to_vivado
  ☆18Updated last year
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated last week
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆66Updated 3 weeks ago
• asyncvlsi / summer2022
  Summer School Week 1 & 2 repo
  ☆11Updated 2 years ago
• ombhilare999 / riscv-core
  A customized RISCV core made using verilog
  ☆19Updated 3 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆114Updated 11 months ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆47Updated 2 weeks ago
• aignacio / nox
  RISC-V Nox core
  ☆61Updated 3 months ago
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆22Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆53Updated 3 weeks ago
• fpgacademy / DESim
  ☆40Updated last year
• tomverbeure / kv260_bringup
  Temporary repo to gather information about the Kria KV260 board
  ☆56Updated 3 years ago
• mattvenn / caravel_user_project
  Zero to ASIC group submission for MPW2
  ☆13Updated last year
• ARC-Lab-UF / intel-training-modules
  ☆38Updated last year
• aesc-silicon / i2c-gpio-expander
  ☆22Updated last week
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆36Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆74Updated 4 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual host model for verilog
  ☆84Updated last month
• freecores / fpu
  Floating Point Unit
  ☆7Updated 10 years ago
• iamrk-vlsi / RISC-V-MYTH-Workshop
  5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !
  ☆11Updated 2 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆70Updated 7 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• sumukhathrey / Verilog_ASIC_Design
  Verilog for ASIC Design
  ☆25Updated 3 years ago
• antmicro / kria-k26-devboard
  Open source AMD Xilinx Kria UltraScale+ SoM baseboard
  ☆40Updated 2 months ago