UofT-HPRC / fake_fpga

Related projects: ⓘ

• ombhilare999 / riscv-core
  A customized RISCV core made using verilog
  ☆17Updated 3 years ago
• Digilent / Zedboard-OLED
  ☆14Updated 2 years ago
• BeagleWire / BeagleWire
  This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/
  ☆11Updated 3 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆65Updated 5 months ago
• altera-opensource / ghrd-socfpga
  ☆26Updated 2 weeks ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆49Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆59Updated last month
• Future-Electronics-Design-Center / Creative-Eval-Board
  Future Electronics Creative Eval Board featuring a Microsemi SmartFusion2 or IGLOO2 FPGA
  ☆15Updated 4 years ago
• sudhamshu091 / Hardware-Description-Languages-for-FPGA-Design
  My HDL activities appear here. This is for my personal use. PPT's copyrights to University of Colorado Boulder.
  ☆14Updated 3 years ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆35Updated last year
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆32Updated 2 months ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆53Updated 4 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆58Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆34Updated 3 months ago
• Ahmad-Zaklouta / VHDL_courses
  courses to learn VHDL
  ☆18Updated 2 years ago
• WajahatRiaz / QuadSPI
  RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.
  ☆15Updated last year
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆23Updated 3 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆37Updated 4 years ago
• fpgacademy / DESim
  ☆37Updated last year
• ChrisPVille / mig_example
  Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
  ☆25Updated 2 years ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆79Updated last year
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆33Updated 2 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual host model for verilog
  ☆75Updated 3 weeks ago
• VedantParanjape / idf-notes-sra
  https://ve0x10.in/idf-notes-sra/
  ☆11Updated 4 years ago
• EECS150 / asic-labs-fa22
  ☆19Updated last year
• alaasal / GPCore
  This is the base repo for our graduation project in AlexU 21
  ☆28Updated 3 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆68Updated 10 months ago
• kole-huang / picorv32_soc
  picorv32_soc, simulation env, FPGA, boot code, RTOS
  ☆14Updated 5 years ago
• kiwih / qtcore-C1
  ☆44Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆92Updated this week