Alternatives and similar repositories for 32-Verilog-Mini-Projects

Users that are interested in 32-Verilog-Mini-Projects are comparing it to the libraries listed below

• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆465Updated 5 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆568Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆379Updated this week
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆362Updated 2 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆432Updated 3 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆323Updated 3 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆422Updated last year
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆38Updated last year
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆223Updated 7 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆152Updated last year
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆130Updated 4 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆280Updated 3 years ago
• TheRA1A / Router1x3
  Router 1x3 design and uvm verification testbach and coverage report
  ☆12Updated 10 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆505Updated 6 months ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆392Updated last year
• Gowtham1729 / Image-Processing
  Image Processing Toolbox in Verilog using Basys3 FPGA
  ☆215Updated 3 months ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆179Updated 7 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,369Updated last week
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆222Updated 2 years ago
• Psichico / Universal_Verification_Methodology
  ☆10Updated 2 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆260Updated 12 years ago
• hxfycy / 1024-point-fft
  Radix-4 1024 point fft in verilog
  ☆11Updated 5 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆641Updated 6 months ago
• abdelazeem201 / ASIC-Design-Roadmap
  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…
  ☆393Updated 2 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆830Updated 6 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆512Updated 3 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆670Updated 2 years ago
• gillianGan / ahb_sram_master
  ☆19Updated 5 years ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆593Updated 7 years ago
• UndefeatedSunny / VLSI-Interview-Questions
  Digital Design verilog tricky problems having industry standards
  ☆26Updated 5 years ago