Alternatives and similar repositories for Cache:

Users that are interested in Cache are comparing it to the libraries listed below

• nikkatsa7 / SpaceInvadersFpgaGame
  Verilog implementation of the classic arcade game Space Invaders for the Zedboard FPGA board
  ☆44Updated 7 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• joewing / memsim
  Memory Simulator and Optimizer
  ☆23Updated 5 years ago
• ChrisPVille / mig_example
  Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
  ☆30Updated 2 years ago
• jvitkauskas / Altera-Cyclone-IV-board-V3.0
  Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board
  ☆126Updated 2 years ago
• HarmonInstruments / hififo
  Harmon Instruments FIFO to PCI Express interface
  ☆11Updated 4 years ago
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 3 months ago
• wzab / vextproj
  VEXTPROJ - the version control friendly system for creation of Vivado projects
  ☆13Updated last year
• nockieboy / gpu
  Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.
  ☆16Updated 2 years ago
• MadLittleMods / vga-simulator
  ☆16Updated last year
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆22Updated 7 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆68Updated this week
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆26Updated 3 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆85Updated 9 months ago
• poucotm / SublimeLinter-contrib-verilator
  👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)
  ☆16Updated 10 months ago
• Future-Electronics-Design-Center / Creative-Eval-Board
  Future Electronics Creative Eval Board featuring a Microsemi SmartFusion2 or IGLOO2 FPGA
  ☆16Updated 5 years ago
• sfmth / ibnalhaytham
  32-bit RISC-V based processor with memory controler
  ☆15Updated 2 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• open-design / riscv-soc-cores
  ☆37Updated 4 years ago
• barbedo / verilog-book
  Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu
  ☆21Updated 6 years ago
• salcanmor / SRAM-tester-for-Cmod-A7-35T
  Tester for IS61WV5128BLL-10BLI SRAM in Cmod A7-35T
  ☆18Updated 6 years ago
• arthurbeggs / riscv-simple
  Computer architecture learning environment using FPGAs
  ☆13Updated 3 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆80Updated this week
• silverfoxy / MIPS-Verilog
  MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.
  ☆23Updated 6 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆32Updated 3 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆25Updated 7 years ago
• robertdunne / FPGA-ARM
  Verilog source code for book: Computer Architecture Tutorial
  ☆25Updated 3 years ago
• mitya1337 / Simple_I2C
  Simple implementation of I2C interface written on Verilog and SystemC
  ☆42Updated 7 years ago
• kooltzh / xilinx-coe-generator
  Python script for generating Xilinx .coe files for RAM initializing
  ☆15Updated 6 years ago