joewing / memsimLinks
Memory Simulator and Optimizer
☆22Updated 6 years ago
Alternatives and similar repositories for memsim
Users that are interested in memsim are comparing it to the libraries listed below
Sorting:
- Centaur, a framework for hybrid CPU-FPGA databases☆27Updated 8 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- ☆63Updated 7 years ago
- Pulp virtual platform☆24Updated 5 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 3 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- FPGA tool performance profiling☆104Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- Visual Simulation of Register Transfer Logic☆109Updated 4 months ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- ☆12Updated 3 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- ☆22Updated 2 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆45Updated 9 months ago
- FPGA implementation of deflate (de)compress RFC 1950/1951☆63Updated 6 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆39Updated 10 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- The Task Parallel System Composer (TaPaSCo)☆116Updated 3 weeks ago
- FPGA Assembly (FASM) Parser and Generator☆99Updated 3 years ago
- ☆59Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago