RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel
☆466Feb 6, 2025Updated last year
Alternatives and similar repositories for RISC-V-Single-Cycle-CPU
Users that are interested in RISC-V-Single-Cycle-CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Digital logic design tool and simulator☆7,903Updated this week
- ☆45Apr 2, 2018Updated 8 years ago
- Simple Yet Powerful RISC-V Computer☆128Jul 12, 2026Updated 3 months ago
- An 8-Bit (mostly) discrete CPU, built in Logisim.☆80Aug 21, 2022Updated 4 years ago
- RV32I single cycle simulation on open-source software Logisim.☆23Oct 8, 2022Updated 4 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- A simulation of Ben Eater's 8-bit CPU in Logisim Evolution (Holy Cross Edition).☆35Aug 20, 2020Updated 6 years ago
- A Simulative MIPS CPU running on Logisim.☆150Jul 17, 2022Updated 4 years ago
- ☆15Jul 27, 2018Updated 8 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,398Sep 7, 2026Updated 2 months ago
- A 32-Bit RISC Processor implemented on Logisim along with a python based assembler.☆18Nov 4, 2017Updated 9 years ago
- 8-bit RISC Processor on Logisim☆14Oct 1, 2020Updated 6 years ago
- PlayStation GPU (WIP)☆17Oct 3, 2023Updated 3 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,636Oct 12, 2026Updated 3 weeks ago
- SERV - The SErial RISC-V CPU☆1,916Aug 25, 2026Updated 2 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,303Oct 13, 2026Updated 3 weeks ago
- Implementation of a RISC-V CPU in Verilog.☆21Jun 27, 2026Updated 4 months ago
- LunaPnR is a place and router for integrated circuits☆48Feb 11, 2026Updated 8 months ago
- TinyTapeout-01 submission repo☆33Nov 28, 2022Updated 3 years ago
- An open-source 32-bit RISC-V soft-core processor☆48Updated this week
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,305Updated this week
- RISC-V RV32IM cpu circuit in Logisim Evolution.☆27Jun 9, 2021Updated 5 years ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- For COD course in USTC, on 2020 Spring, prof. Chao Wang☆10Sep 18, 2020Updated 6 years ago
- Digital logic designer and simulator☆135Sep 16, 2026Updated last month
- Verilog implementation of Bresenham's line drawing algorithm.☆14May 11, 2026Updated 5 months ago
- Implementation of RV32I in Logisim-evolution.☆26Sep 19, 2023Updated 3 years ago
- ☆23Jul 12, 2024Updated 2 years ago
- Logisim designs for teaching computer organization. https://mkayaalp.net/computer-organization-logisim☆29Jun 17, 2021Updated 5 years ago
- Logisim CPU.☆33Nov 23, 2022Updated 3 years ago
- Simulation in Logisim-Evolution HC☆34Jun 30, 2021Updated 5 years ago
- PandaForth, a port of CamelForth to the GBA by Torlus☆10Sep 3, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- original 8bit CPU of ICF3-Z☆12Feb 20, 2020Updated 6 years ago
- A simple RISC-V processor for use in FPGA designs.☆288Aug 19, 2024Updated 2 years ago
- RISC-V CPU for OpenFPGAs, in Icestudio☆108Jun 2, 2024Updated 2 years ago
- A version of the Lisp programming language for RISC-V based boards.☆31Jan 12, 2025Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Dec 3, 2025Updated 11 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆382Dec 2, 2025Updated 11 months ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆34Aug 28, 2024Updated 2 years ago