Alternatives and similar repositories for emulsiV

Users that are interested in emulsiV are comparing it to the libraries listed below

• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆389Updated this week
• riscv-non-isa / riscv-arch-test
  ☆567Updated last week
• mikeroyal / RISC-V-Guide
  RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-…
  ☆582Updated last year
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆223Updated 4 years ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆148Updated last month
• stevehoover / LF-Building-a-RISC-V-CPU-Core
  ☆390Updated 3 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆487Updated last month
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆268Updated this week
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆191Updated 3 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆259Updated 2 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆772Updated this week
• riscv / learn
  Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
  ☆934Updated 5 months ago
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆357Updated 11 months ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆140Updated 2 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆238Updated 7 months ago
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆201Updated last year
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆642Updated 3 weeks ago
• embench / embench-iot
  The main Embench repository
  ☆284Updated 9 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 6 months ago
• cccriscv / mini-riscv-os
  Build a minimal multi-tasking OS kernel for RISC-V from scratch
  ☆451Updated 2 years ago
• riscv-software-src / riscv-tests
  ☆1,024Updated last week
• Mariotti94 / WebRISC-V
  WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
  ☆147Updated 2 weeks ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆175Updated 2 months ago
• johnwinans / rvalp
  RISC-V Assembly Language Programming
  ☆234Updated 10 months ago
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆91Updated 4 years ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆214Updated last month
• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆142Updated last year
• splinedrive / lets_build_a_compiler_for_riscv
  A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
  ☆113Updated 2 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,041Updated 3 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆274Updated 4 months ago