Major project - kannada LLM for farmers
☆12May 20, 2024Updated 2 years ago
Alternatives and similar repositories for hardware-accelerator-for-LLM
Users that are interested in hardware-accelerator-for-LLM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Accelerator for LLM Based on Chisel3☆15Jul 16, 2026Updated 3 months ago
- The Reconfigurable Solver for QP☆13Apr 19, 2023Updated 3 years ago
- XtraMAC code repo (Accepted by ISCA2026)☆33Sep 9, 2026Updated 2 months ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆17Aug 25, 2023Updated 3 years ago
- ☆15Jul 7, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- MLIR-based Compiler for CGRA SoC☆19Sep 21, 2026Updated last month
- 这里汇总了我在学习道路上的文档、代码、文件或推文。This is a collection of documents, code, files, or articles written by me.☆15Apr 26, 2026Updated 6 months ago
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆19Dec 16, 2017Updated 8 years ago
- An implementation of the Advanced Encryption Standard (AES) encryption algorithm using Verilog supporting AES-128, AES-192, and AES-256 e…☆18Jun 7, 2025Updated last year
- A repository for the Major Project for the Case Studies Course☆25May 28, 2024Updated 2 years ago
- Lock-free work stealing deque written in C. This is implemented after Chapter 16 of "The Art of Multiprocessor Programming."☆19May 27, 2011Updated 15 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆13Dec 7, 2023Updated 2 years ago
- My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA☆13Jun 26, 2018Updated 8 years ago
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆23Aug 24, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis☆13Mar 8, 2022Updated 4 years ago
- 16 bit serial multiplier in SystemVerilog☆13Oct 13, 2018Updated 8 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆136Jun 27, 2023Updated 3 years ago
- Collection of kernel accelerators optimised for LLM execution☆35Feb 26, 2026Updated 8 months ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆18Aug 2, 2019Updated 7 years ago
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆45Aug 9, 2025Updated last year
- PAM4 Receiver Implementation with AI-Driven HDL Code Generation☆12Aug 15, 2025Updated last year
- Cryptography accelerator core (for AES128/AES256 and SHA256) designed in Chisel3, primarily targeting ASIC platforms.☆11Jan 11, 2021Updated 5 years ago
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆29Jun 30, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Accelerator RTL inspired by VEGETA [HPCA'23] and MicroScopiQ [ISCA'25]☆17Nov 11, 2025Updated last year
- Gomoku AI (Alpha Zero) implemented by pytorch and onnxruntime.☆10Dec 23, 2025Updated 10 months ago
- Open Source Projects from Pallas Lab☆21Oct 10, 2021Updated 5 years ago
- Fast Floating Point Operators for High Level Synthesis☆26Feb 23, 2023Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆90Sep 29, 2025Updated last year
- A repository for the Major Project for the Case Studies Course in BDSA☆55May 28, 2024Updated 2 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆35Nov 6, 2026Updated last week
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆11Dec 18, 2023Updated 2 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆17Mar 14, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆24Mar 10, 2024Updated 2 years ago
- ☆19May 21, 2026Updated 5 months ago
- ☆20Mar 21, 2023Updated 3 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 5 years ago
- Model LLM inference on single-core dataflow accelerators☆22Dec 16, 2025Updated 10 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Synopsys tools.☆16Jun 28, 2025Updated last year
- ☆23Feb 18, 2025Updated last year
Are these results useful?