This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
☆34May 23, 2026Updated 5 months ago
Alternatives and similar repositories for VLSI-Design-Verification-Projects
Users that are interested in VLSI-Design-Verification-Projects are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆52Jul 11, 2025Updated last year
- This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory,…☆18Sep 5, 2024Updated 2 years ago
- Verilog code for a low power RFID chip that will communicate with I2C sensors.☆13Apr 18, 2014Updated 12 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsin…☆11Nov 16, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- an attempt to implement CRYSTALS-Kyber PQC to Verilog☆12Jan 9, 2025Updated last year
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- ☆11Feb 11, 2019Updated 7 years ago
- This repository contains solutions to the practice problems available on the HDLBits platform, which cover a wide range of topics in Digi…☆13Apr 24, 2023Updated 3 years ago
- Cache-accel: FPGA Accelerated Multi-Core Cache Simulator☆14Mar 12, 2022Updated 4 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆60Mar 3, 2024Updated 2 years ago
- Semiconductor Packaging Fundamentals☆45May 19, 2025Updated last year
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- UVM Verification Environment for the CVFPU☆26Aug 27, 2026Updated 2 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 3 months ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆15Sep 9, 2022Updated 4 years ago
- Verilog HDL code and Finite State Machine (FSM) for a simple ATM☆13Jul 26, 2020Updated 6 years ago
- vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/C…☆20Mar 28, 2026Updated 7 months ago
- Design and UVM Verification of an ALU☆13Jun 14, 2024Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Synopsys tools.☆16Jun 28, 2025Updated last year
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆19Sep 15, 2020Updated 6 years ago
- 32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog☆18Aug 27, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A plugin to allow Jenkins Steps with Cadence vManager API☆10Jan 15, 2026Updated 9 months ago
- FIR and LMS filter implementations in FPGAs☆15Nov 18, 2019Updated 6 years ago
- CORE-V MCU UVM Environment and Test Bench☆29Jul 19, 2024Updated 2 years ago
- Implementation of a low-pass FIR filter in Verilog HDL.☆12Apr 12, 2024Updated 2 years ago
- UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.☆12Dec 9, 2023Updated 2 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- This course explains the basics of Tcl scripting language, which is embedded in almost all EDA tools and can be used to automate many ope…☆20Jul 11, 2026Updated 3 months ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆19Dec 12, 2025Updated 10 months ago
- AMIQ Externally Controlled Test Bench☆12Jan 13, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆21Apr 27, 2024Updated 2 years ago
- Synthesizable FIR filters in VHDL☆16Jul 19, 2019Updated 7 years ago
- Design and implementation of a reconfigurable FIR filter in FPGA☆17Sep 26, 2022Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆50May 10, 2024Updated 2 years ago
- Lecture about FIR filter on an FPGA☆18May 15, 2024Updated 2 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 6 years ago
- SystemVerilog examples and projects☆21Jun 10, 2025Updated last year