UART - RTL Design and Verification
☆13Sep 6, 2021Updated 5 years ago
Alternatives and similar repositories for UART-protocol
Users that are interested in UART-protocol are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Voting machine implemented in verilog☆10Apr 8, 2023Updated 3 years ago
- ☆11Feb 11, 2019Updated 7 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- 16 bit CPU created in Vivado with Verilog☆23Jun 30, 2022Updated 4 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 7 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with single port sync RAM.☆11Jan 31, 2025Updated last year
- The Repository contains the code of various Digital Circuits☆14Aug 7, 2023Updated 3 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 5 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆40Mar 13, 2025Updated last year
- [PACIS 2024] The official repo for the paper: "Phase Space Reconstructed Neural Ordinary Differential Equations Model for Stock Price For…☆10May 21, 2025Updated last year
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- Basic scripts for Synopsys Design Compiler and Synopsys IC Compiler☆10Mar 31, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆19Dec 12, 2025Updated 11 months ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆22Nov 26, 2018Updated 7 years ago
- Config files for my GitHub profile.☆14Apr 21, 2025Updated last year
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧，控制DA输出相应正弦信号☆10Jul 10, 2019Updated 7 years ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆25Dec 11, 2023Updated 2 years ago
- Hardware implementation of the ChaCha20-Poly1305 AEAD construction☆15Oct 8, 2020Updated 6 years ago
- ☆13May 21, 2019Updated 7 years ago
- This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory,…☆19Sep 5, 2024Updated 2 years ago
- Try to implement GCM-AES encryption algorithm on FPGA hardware and test it by software.☆10May 31, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆12May 15, 2024Updated 2 years ago
- Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.☆13Jan 15, 2022Updated 4 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆17Sep 23, 2020Updated 6 years ago
- 基于Verilog实现的串口发送程序，带奇偶校验位。☆12Aug 23, 2019Updated 7 years ago
- 32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog☆18Aug 27, 2020Updated 6 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆13Sep 3, 2019Updated 7 years ago
- python library for 2d homographies☆15Jan 22, 2021Updated 5 years ago
- ☆10Feb 18, 2023Updated 3 years ago
- 108下 計算機組織 Computer Organization 李毅郎☆13Feb 22, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- ☆22Apr 4, 2024Updated 2 years ago
- A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.☆17Mar 25, 2023Updated 3 years ago
- 使用FPGA实现的一个I2C从机模块，可读可写，可改设备地址，可扩展，模拟摄像头内部的sensor☆10Jun 26, 2023Updated 3 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13May 5, 2015Updated 11 years ago
- ☆16May 30, 2021Updated 5 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆39May 7, 2024Updated 2 years ago
Are these results useful?