lorentsinani / 16bitCPU-Verilog
16 bit CPU created in Vivado with Verilog
☆18Updated 2 years ago
Alternatives and similar repositories for 16bitCPU-Verilog:
Users that are interested in 16bitCPU-Verilog are comparing it to the libraries listed below
- Single Cycle MIPS Pipelined Processor using Verilog☆14Updated 3 years ago
- ☆16Updated last year
- ☆109Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆75Updated last year
- ☆16Updated last year
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆42Updated 4 years ago
- ☆9Updated 2 years ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- ☆17Updated last year
- ☆40Updated last year
- ☆43Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆88Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- An 8 input interrupt controller written in Verilog.☆26Updated 13 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- Single Cycle RISC MIPS Processor☆32Updated 3 years ago
- A complete UVM TB for verification of single port 64KB RAM☆15Updated 4 years ago
- ☆10Updated last year
- System Verilog using Functional Verification☆10Updated last year
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆9Updated 7 months ago
- opensource EDA tool flor VLSI design☆32Updated last year
- Verilog Code for I2C Protocol☆17Updated 4 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆11Updated 9 months ago
- ☆16Updated last year
- UVM Testbench to verify serial transmission of data between SPI master and slave☆44Updated 4 years ago
- ☆27Updated 11 months ago
- ☆22Updated last year