RaviVijay / awesome-dl-hw-resources
A curated list of awesome hardware/chip design resources for deep learning
☆49Updated 7 years ago
Alternatives and similar repositories for awesome-dl-hw-resources
Users that are interested in awesome-dl-hw-resources are comparing it to the libraries listed below
Sorting:
- Verilog/SystemVerilog Guide☆66Updated last year
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆16Updated last year
- Curriculum for a university course to teach chip design using open source EDA tools☆68Updated last year
- ☆58Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆18Updated 2 years ago
- A curated list of awesome open source hardware design tools☆80Updated 6 months ago
- Resources for my first book☆17Updated last year
- Universal Memory Interface (UMI)☆145Updated this week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- A curated list of awesome HDL, libraries, typical implementation and references.☆37Updated 8 years ago
- An overview of TL-Verilog resources and projects☆78Updated last month
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 6 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Complete tutorial code.☆20Updated last year
- ☆34Updated 5 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆48Updated 3 months ago
- This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …☆34Updated last month
- ☆21Updated 6 months ago
- A curated list of awesome resources for HDL design and verification☆146Updated this week
- ☆29Updated last year
- ☆79Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆77Updated this week
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆178Updated this week
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆62Updated 8 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆57Updated 2 months ago
- Open source ISS and logic RISC-V 32 bit project☆52Updated 3 weeks ago
- Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos Schoo…☆47Updated 3 years ago