PXVI / amba_apb_ip_master_slave_verilogView external linksLinks
The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )
☆17Dec 12, 2025Updated 2 months ago
Alternatives and similar repositories for amba_apb_ip_master_slave_verilog
Users that are interested in amba_apb_ip_master_slave_verilog are comparing it to the libraries listed below
Sorting:
- ☆55Jun 19, 2021Updated 4 years ago
- ☆10Aug 12, 2021Updated 4 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago
- ☆18Jan 19, 2026Updated 3 weeks ago
- PC sampling profiler for Cortex-M MCUs☆13Jan 23, 2026Updated 3 weeks ago
- Embedded facial recognition system involving PYNQ board, Webcam, and HDMI output.☆11May 10, 2018Updated 7 years ago
- Verilog Gate level Implementation of floating point arithmetic as per IEEE 754☆10May 18, 2021Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- Python framework to solve crypto problems using grainofsalt and cryptominisat☆14May 24, 2022Updated 3 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- ☆13Sep 5, 2022Updated 3 years ago
- stm32的USB-DFU上位机工具源码(MFC),基于ST官方DfuSe-v3.0.4 ,实现了hex转dfu,解决官方代码的一些bug☆13Aug 9, 2017Updated 8 years ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆18Oct 28, 2024Updated last year
- Numerical Run Length Encoding and Arithmetic in Cython☆19Jan 28, 2026Updated 2 weeks ago
- UltraZed Edition examples☆12Oct 29, 2017Updated 8 years ago
- Basic floating-point components for RISC-V processors☆11Aug 13, 2017Updated 8 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆14Nov 19, 2023Updated 2 years ago
- 010 Editor Keygen☆16May 14, 2018Updated 7 years ago
- A set of small Verilog projects, to simulate and implement on FPGA development boards☆15Mar 5, 2018Updated 7 years ago
- CMSIS SVD editor☆14Mar 14, 2020Updated 5 years ago
- Miscellaneous prototype hardware that wasn't major enough to warrant a dedicated repo☆17Aug 1, 2025Updated 6 months ago
- 电子科技大学示范性微电子学院微嵌课程配套代码☆15Dec 10, 2025Updated 2 months ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- From datasheet (pdf) to SVD... to then be fed into svd2rust☆10May 26, 2022Updated 3 years ago
- Exercise test framework for Regular Expression tutorial☆11Mar 29, 2018Updated 7 years ago
- A plugin that enables Custom Field of type DateTime (native one have only Date, not Time)☆15Jun 11, 2020Updated 5 years ago
- ☆13Apr 24, 2022Updated 3 years ago
- SEGGER-RTT Terminal program using CMSIS-DAP (DAPLink)☆14Jun 23, 2018Updated 7 years ago
- language-independent printf test suite☆14Oct 7, 2018Updated 7 years ago
- AES加解密算法的C实现☆13Aug 1, 2016Updated 9 years ago
- USB-PD-3.1-Verilog☆17Apr 22, 2024Updated last year
- ☆14Apr 24, 2023Updated 2 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 4 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆20Nov 26, 2018Updated 7 years ago
- UDP and TCP echo servers using lwIP RAW API running on Xilinx Zynq Platform☆12Apr 15, 2014Updated 11 years ago
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆12Jan 21, 2022Updated 4 years ago
- Benchmarks for High-Level Synthesis☆10Mar 17, 2023Updated 2 years ago
- Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher☆17Feb 27, 2024Updated last year
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆20Dec 11, 2023Updated 2 years ago