Wishbone plumbing written in Chisel3
☆10Dec 19, 2024Updated last year
Alternatives and similar repositories for WbPlumbing
Users that are interested in WbPlumbing are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Jan 15, 2026Updated 9 months ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- ☆24Feb 11, 2021Updated 5 years ago
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated last year
- Hardware Description from Technical Documentation☆15Oct 9, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- For contributions of Chisel IP to the chisel community.☆73Sep 17, 2026Updated last month
- An example of on-boarding a PIO block in with duh and wake☆12Nov 18, 2020Updated 5 years ago
- Chisel Examples for the iCESugar FPGA Board☆12May 4, 2021Updated 5 years ago
- PipeProof☆11Dec 18, 2019Updated 6 years ago
- ☆10Dec 28, 2020Updated 5 years ago
- Modern cryptography primitives implemented in Scratch, via Boiga☆13Jul 16, 2022Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆49Feb 12, 2026Updated 8 months ago
- Simple RS232 UART☆12Apr 3, 2016Updated 10 years ago
- RISCV SoftCPU Contest 2018☆14Nov 17, 2018Updated 7 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆36Sep 30, 2020Updated 6 years ago
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 4 years ago
- A programming language for writing constraint-based integrated circuit layout generators☆17Updated this week
- A DSL for Systolic Arrays☆86Dec 14, 2018Updated 7 years ago
- ☆27Sep 3, 2020Updated 6 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Jan 2, 2019Updated 7 years ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆16Aug 30, 2023Updated 3 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Companion code and schematics for my breadboard Z80 series☆11Dec 6, 2020Updated 5 years ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated last month
- ☆14Dec 19, 2025Updated 10 months ago
- CLI for WaveDrom☆68Feb 22, 2024Updated 2 years ago
- Chisel Cheatsheet☆37Apr 13, 2023Updated 3 years ago
- A PCIe RTL implementation☆26Aug 16, 2026Updated 2 months ago
- My MEng thesis code - verifying a security property for an SoC with Rosette☆18Jun 9, 2021Updated 5 years ago
- git clone from https://gnunet.org/svn/libmicrohttpd/☆13Feb 20, 2013Updated 13 years ago
- Source for my lab notebook☆12Sep 22, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog AST☆19Dec 2, 2023Updated 2 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆22Dec 14, 2020Updated 5 years ago
- bpm.is sauce☆10Nov 5, 2021Updated 4 years ago
- Simulating Verilog designs on a microcontroller☆14Sep 13, 2022Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Sep 19, 2018Updated 8 years ago
- ☆24Feb 3, 2026Updated 8 months ago
- Free, open-source, cross-platform desktop Markdown text editor with live preview, string interpolation, and math.☆12Jun 3, 2023Updated 3 years ago