Alternatives and similar repositories for SITLINV-FPGA_Board

Users that are interested in SITLINV-FPGA_Board are comparing it to the libraries listed below

• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆87Updated 2 years ago
• ZipCPU / sdr
  A basic Soft(Gate)ware Defined Radio architecture
  ☆96Updated last year
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆110Updated 8 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆30Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆120Updated 4 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆46Updated 4 years ago
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆90Updated 3 months ago
• controlpaths / blog
  Projects published on controlpaths.com and hackster.io
  ☆42Updated 3 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆57Updated last year
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated this week
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆69Updated 8 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆67Updated 3 weeks ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆42Updated 8 months ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆74Updated 3 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆95Updated 5 years ago
• efard / DSPHDL
  Digital Signal Processing and Well-Known Modulations on HDL
  ☆41Updated 4 months ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆46Updated 5 years ago
• 0xArt / Tiny_But_Mighty_I2C_Master_Verilog
  I2C Master Verilog module
  ☆34Updated 4 months ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆96Updated last year
• openXC7 / demo-projects
  Demo projects for various Kintex FPGA boards
  ☆62Updated 4 months ago
• sam210723 / fpga
  Collection of projects for various FPGA development boards
  ☆46Updated last year
• enjoy-digital / litex-acorn-baseboard
  LiteX development baseboards arround the SQRL Acorn.
  ☆70Updated 6 months ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆27Updated 6 years ago
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆32Updated 9 years ago
• alberto-grl / 1bitSDR
  Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
  ☆106Updated 5 years ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆71Updated 4 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆46Updated last year