MPA-MLF / ExercisesLinks
Lab files of Machine Learning Fundamentals course taught at the Brno University of Technology
☆10Updated 9 months ago
Alternatives and similar repositories for Exercises
Users that are interested in Exercises are comparing it to the libraries listed below
Sorting:
- Open Logic FPGA Standard Library☆833Updated this week
- A git-friendly Vivado wrapper☆243Updated last year
- lowRISC Style Guides☆472Updated last month
- The UVM written in Python☆489Updated this week
- Contains the code examples from The UVM Primer Book sorted by chapters.☆588Updated 3 years ago
- 100 Days of RTL☆403Updated last year
- Verilog UART☆515Updated 9 months ago
- cocotb: Python-based chip (RTL) verification☆2,185Updated this week
- VUnit is a unit testing framework for VHDL/SystemVerilog☆804Updated this week
- Verilog I2C interface for FPGA implementation☆664Updated 9 months ago
- Various HDL (Verilog) IP Cores☆852Updated 4 years ago
- A collection of Master XDC files for Digilent FPGA and Zynq boards.☆639Updated last year
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆22Updated 4 months ago
- Verilog AXI stream components for FPGA implementation☆844Updated 9 months ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆722Updated last week
- Awesome ASIC design verification☆337Updated 3 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆517Updated last month
- SystemVerilog to Verilog conversion☆681Updated 3 weeks ago
- training labs and examples☆439Updated 3 years ago
- Reference examples and short projects using UVM Methodology☆285Updated 3 years ago
- synthesiseable ieee 754 floating point library in verilog☆701Updated 2 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,373Updated last week
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆26Updated 11 months ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆550Updated 2 years ago
- Common SystemVerilog components☆686Updated this week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆678Updated this week
- Bus bridges and other odds and ends☆612Updated 8 months ago
- ☆653Updated 4 months ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,281Updated this week
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆417Updated 2 weeks ago