MPA-MLF / ExercisesLinks
Lab files of Machine Learning Fundamentals course taught at the Brno University of Technology
☆10Updated 4 months ago
Alternatives and similar repositories for Exercises
Users that are interested in Exercises are comparing it to the libraries listed below
Sorting:
- lowRISC Style Guides☆440Updated last month
- Open Logic FPGA Standard Library☆671Updated 2 weeks ago
- Verilog UART☆494Updated 4 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆783Updated 2 months ago
- Verilog I2C interface for FPGA implementation☆625Updated 4 months ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆624Updated 3 months ago
- 32-bit Superscalar RISC-V CPU☆1,053Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,321Updated this week
- Verilog AXI stream components for FPGA implementation☆812Updated 4 months ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆798Updated 2 weeks ago
- Instructions & Assignments for COD Lab - UE22EC352A☆4Updated 7 months ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,802Updated this week
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆582Updated 7 years ago
- Various HDL (Verilog) IP Cores☆818Updated 4 years ago
- Random instruction generator for RISC-V processor verification☆1,136Updated last month
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,582Updated last month
- Verilog AXI components for FPGA implementation☆1,762Updated 4 months ago
- 100 Days of RTL☆380Updated 10 months ago
- Common SystemVerilog components☆634Updated this week
- synthesiseable ieee 754 floating point library in verilog☆657Updated 2 years ago
- cocotb: Python-based chip (RTL) verification☆2,025Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,090Updated last month
- uvm_starter is a simple template for starting uvm projects☆10Updated 5 months ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆556Updated 3 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆503Updated 7 months ago
- An Open-source FPGA IP Generator☆937Updated this week
- Scala based HDL☆1,819Updated this week
- Digital Design with Chisel☆845Updated last week
- A git-friendly Vivado wrapper☆235Updated last year
- SystemVerilog to Verilog conversion☆645Updated 3 weeks ago