JeffreySamuel / canny_edge_detection_in_FPGA

Related projects ⓘ

Alternatives and complementary repositories for canny_edge_detection_in_FPGA

• DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm
  The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…
  ☆29Updated 6 months ago
• KooJaack / Canny-Edge-Detection-on-FPGA
  Implementation of Canny Edge Detection on Cyclone IV. To run project you need Quartus and ModelSim.
  ☆10Updated 4 years ago
• BambooWhispering / FPGA-image-simulation
  FPGA图像处理仿真平台
  ☆25Updated 2 years ago
• xiesicong / fpga_sobel_ov5640_hdmi
  fpga跑sobel识别算法
  ☆26Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆90Updated 4 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆33Updated 6 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆49Updated 2 years ago
• Starrynightzyq / ZYNQ-PYNQ-Z2-Gobang
  2018第二届全国大学生FPGA创新设计邀请赛的作品
  ☆57Updated 5 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆45Updated 4 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆10Updated 6 months ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二，紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆120Updated last week
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆100Updated 10 years ago
• Thes0me / pango_video_local_dimming
  2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件
  ☆31Updated last year
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆37Updated 4 years ago
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆32Updated 3 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆111Updated 3 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆35Updated 2 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆45Updated 3 years ago
• iharbour-heyaonan / FPGA_image_process
  FPGA实现简单的图像处理算法
  ☆41Updated last year
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆159Updated 7 months ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆45Updated 3 years ago
• padhi499 / Image-Classification-using-CNN-on-FPGA
  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
  ☆118Updated 3 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 6 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆22Updated 5 years ago
• ForrestBlue / cortexm0ds
  ☆52Updated 8 years ago
• gillianGan / ahb_sram_master
  ☆18Updated 4 years ago
• jiaowushuang / fpga_design
  这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统
  ☆80Updated 7 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆31Updated 4 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆55Updated 9 months ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆50Updated 10 years ago