JeffreySamuel / canny_edge_detection_in_FPGAView external linksLinks
In this project, Canny edge detection, one of the efficient edge detection algorithms is implemented on a Zedboard FPGA using verilog. The input image is stored on a PC and fed to the FPGA. The output processed image is displayed on a VGA monitor.
☆23Oct 15, 2021Updated 4 years ago
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