Alternatives and similar repositories for complex_multiplier:

Users that are interested in complex_multiplier are comparing it to the libraries listed below

• catkira / CIC
  HDL code for a complex multiplier with AXI stream interface
  ☆16Updated 2 years ago
• catkira / DDS
  HDL code for a DDS (direct digital synthesizer) with AXI stream interface
  ☆18Updated last year
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆21Updated last year
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆45Updated last year
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• analogdevicesinc / HighSpeedConverterToolbox
  MATLAB toolbox for ADI high speed converter products
  ☆19Updated this week
• MicroPhase / antsdr_standalone
  Standalone application based on ADI hdl and no_OS for ANTSDR.
  ☆19Updated last year
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆12Updated this week
• farbius / dsp_xilinx_ip
  Some basic DSP algorithms implemented with xilinx IP cores with explanation, Verilog testbenches and modelling in Python
  ☆33Updated 2 years ago
• strath-sdr / rfsoc_qsfp_offload
  RFSoC QSFP Data Offload Design with GNU Radio
  ☆17Updated 2 months ago
• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆26Updated 4 months ago
• oscimp / oscimpDigital
  OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing
  ☆52Updated 3 weeks ago
• analogdevicesinc / jesd-eye-scan-gtk
  JESD204 Eye Scan Visualization Utility
  ☆12Updated 3 months ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• analogdevicesinc / TransceiverToolbox
  MATLAB toolbox for ADI transceiver products
  ☆59Updated last month
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• coralhu123 / KC705-AD9371
  The implementation of AD9371 on KC705
  ☆20Updated 4 years ago
• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆113Updated last year
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆18Updated 6 months ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆51Updated 11 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆41Updated last month
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆97Updated last year
• srsran / zynq_timestamping
  Open source Zynq timestamping implementation from Software Radio Systems (SRS)
  ☆64Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆46Updated last year
• MicroPhase / antsdr-pynq
  pynq framework for antsdr
  ☆34Updated 8 months ago
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆92Updated 7 months ago
• Grootzz / AD9361_TX_MSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
  ☆54Updated 5 years ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆59Updated last year