FPGA-Research-Manchester / FPGAVirusScanner
Program to scan for malicious FPGA designs.
☆13Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for FPGAVirusScanner
- Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)☆14Updated 3 years ago
- Open Source AES☆31Updated 7 months ago
- How to use the Intel JTAG primitive without using virtual JTAG☆16Updated 3 years ago
- PCIe analyzer experiments☆45Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- ☆14Updated 2 years ago
- Exploring gate level simulation☆56Updated 2 years ago
- ☆12Updated 2 years ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆26Updated last year
- Waveform Generator☆11Updated 2 years ago
- ☆32Updated last year
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆21Updated 5 years ago
- ☆29Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆31Updated 2 years ago
- Chisel NVMe controller☆13Updated last year
- USB virtual model in C++ for Verilog☆28Updated 3 weeks ago
- ☆22Updated 2 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 2 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆23Updated 2 years ago
- ☆57Updated 3 years ago
- S3GA: a simple scalable serial FPGA☆10Updated last year
- Experiments with Yosys cxxrtl backend☆46Updated 10 months ago
- My notes for DDR3 SDRAM controller☆24Updated last year
- User-friendly explanation of Yosys options☆111Updated 3 years ago
- RISC-V RV32I CPU written in verilog☆10Updated 4 years ago
- Another size-optimized RISC-V CPU for your consideration.☆47Updated last week
- KiCad symbol library for sky130 and gf180mcu PDKs☆30Updated 9 months ago
- Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…☆44Updated last week
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 3 years ago
- Virtual development board for HDL design☆39Updated last year