Alternatives and similar repositories for liberty_training

Users that are interested in liberty_training are comparing it to the libraries listed below

• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆96Updated 6 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆70Updated 5 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• freecores / jpegencode
  JPEG Encoder Verilog
  ☆77Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆65Updated 5 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆65Updated last year
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 10 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆77Updated 13 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆120Updated 11 years ago
• ForrestBlue / cortexm0ds
  ☆68Updated 9 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆173Updated this week
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆71Updated 4 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆145Updated 9 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆75Updated 11 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆60Updated 3 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• NukaCola-Quantum / MBIST-verilog
  A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated
  ☆19Updated 6 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆68Updated 5 years ago
• freecores / robust_axi2apb
  Generic AXI to APB bridge
  ☆13Updated 11 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆92Updated last year
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆43Updated 5 years ago
• ic7x24 / verilog-mini-demo
  Verilog极简教程
  ☆37Updated 6 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆39Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆58Updated last year