andrewsil1 / NexysPsram
AXI PSRAM Controller IP for use with Digilent Nexys 4
☆10Updated 2 years ago
Alternatives and similar repositories for NexysPsram:
Users that are interested in NexysPsram are comparing it to the libraries listed below
- Universal Advanced JTAG Debug Interface☆17Updated 9 months ago
- Advanced Debug Interface☆13Updated 3 weeks ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated 3 weeks ago
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- Wishbone <-> AXI converters☆14Updated 9 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 4 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆34Updated 7 years ago
- Extensible FPGA control platform☆57Updated last year
- hdmi-ts Project☆13Updated 7 years ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- Wishbone to AXI bridge (VHDL)☆40Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- PulseRain FP51-1T MCU core☆9Updated 7 years ago
- JTAG Test Access Port (TAP)☆32Updated 10 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- ☆21Updated 7 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- Verilog FT245 to AXI stream interface☆28Updated 6 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆27Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- USB serial device (CDC-ACM)☆37Updated 4 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆24Updated 6 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆54Updated 7 years ago
- SystemVerilog Logger☆17Updated 2 years ago