Alternatives and similar repositories for Graphical-Micro-Architecture-Simulator

Users that are interested in Graphical-Micro-Architecture-Simulator are comparing it to the libraries listed below

• Mariotti94 / WebRISC-V
  WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
  ☆147Updated last month
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆68Updated 2 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆142Updated 2 years ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆149Updated last month
• johnwinans / riscv-toolchain-install-guide
  How to download & install qemu a toolchain suitable for building and running freestanding RISC-V C/C++ programs
  ☆56Updated last year
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆31Updated last month
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 8 months ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆133Updated last month
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆223Updated 4 years ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆107Updated 4 years ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆191Updated 3 weeks ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆181Updated 3 weeks ago
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆91Updated 6 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆102Updated 2 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆192Updated 3 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆260Updated 2 months ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆109Updated last month
• riscv / riscv-aia
  ☆90Updated 3 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆137Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆111Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆240Updated 8 months ago
• ARM-software / tarmac-trace-utilities
  Tools for analyzing and browsing Tarmac instruction traces.
  ☆76Updated last month
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆269Updated last week
• merledu / nucleusrv
  NucleusRV - A 32-bit 5 staged pipelined risc-v core.
  ☆66Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆147Updated 8 months ago
• arm-university / Modern-System-on-Chip-Design-on-Arm
  A textbook on system on chip design using Arm Cortex-A
  ☆32Updated last month
• stnolting / riscv-gcc-prebuilt
  📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
  ☆104Updated 4 months ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆51Updated 6 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆107Updated this week