Alternatives and similar repositories for Graphical-Micro-Architecture-Simulator

Users that are interested in Graphical-Micro-Architecture-Simulator are comparing it to the libraries listed below

• Mariotti94 / WebRISC-V
  WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
  ☆164Updated 5 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 2 months ago
• arm-university / Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers
  A textbook on understanding system on chip design
  ☆60Updated 7 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆158Updated last month
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆40Updated 7 months ago
• five-embeddev / riscv-scratchpad
  RISC-V Scratchpad
  ☆74Updated 3 years ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆153Updated 4 months ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆57Updated last week
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated 3 weeks ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆205Updated last week
• ARM-software / tarmac-trace-utilities
  Tools for analyzing and browsing Tarmac instruction traces.
  ☆81Updated 3 months ago
• riscv / riscv-aia
  ☆99Updated last week
• johnwinans / riscv-toolchain-install-guide
  How to download & install qemu a toolchain suitable for building and running freestanding RISC-V C/C++ programs
  ☆59Updated last year
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆227Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• n-kremeris / verilator_basics
  ☆72Updated 2 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆77Updated 3 weeks ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆186Updated last year
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆95Updated 5 years ago
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆96Updated 6 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 7 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated 5 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆109Updated 4 years ago
• os-fpga / Virtual-FPGA-Lab
  This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…
  ☆237Updated 8 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 4 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆53Updated last week
• embench / embench-iot
  The main Embench repository
  ☆301Updated last year
• chipsalliance / VeeR-ISS
  ☆151Updated 2 years ago
• chipsalliance / riscv-fw-infrastructure
  SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...
  ☆30Updated 4 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆154Updated last year