jamieiles / oldland-cpuLinks
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
☆126Updated 9 years ago
Alternatives and similar repositories for oldland-cpu
Users that are interested in oldland-cpu are comparing it to the libraries listed below
Sorting:
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆150Updated 9 years ago
- The Easy 8-bit Processor☆184Updated 11 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- An attempt at a small Verilog implementation of the original Apple 1 on an FPGA☆150Updated 2 months ago
- A simple GPU on a TinyFPGA BX☆81Updated 7 years ago
- public domain tools for FPGAs☆331Updated 8 years ago
- IBM PC Compatible SoC for a commercially available FPGA board☆72Updated 9 years ago
- A CPU on an FPGA that you can play Zork on☆51Updated 8 years ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆312Updated 2 years ago
- An Open Source configuration of the Arty platform☆132Updated last year
- A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.☆205Updated 4 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Open source implementation of a x86 processor☆330Updated 7 years ago
- ☆61Updated 2 years ago
- A FPGA core for a simple SDRAM controller.☆123Updated 4 years ago
- A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals☆246Updated 7 years ago
- MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD☆230Updated 9 months ago
- LIB:Library for interacting with an FPGA over USB☆85Updated 4 years ago
- A pipelined RISCV implementation in VHDL☆97Updated 7 years ago
- The Zylin ZPU☆244Updated 10 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆412Updated 3 weeks ago
- The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.☆78Updated 13 years ago
- Basic RISC-V CPU implementation in VHDL.☆171Updated 5 years ago
- CMod-S6 SoC☆43Updated 7 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- PanoLogic Zero Client G1 reverse engineering info☆75Updated last year
- A VHDL frontend for Yosys☆104Updated 8 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆111Updated 6 years ago
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 7 years ago