Alternatives and similar repositories for oldland-cpu

Users that are interested in oldland-cpu are comparing it to the libraries listed below

• Domipheus / TPU
  TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…
  ☆148Updated 8 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 4 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆106Updated 10 years ago
• inforichland / freezing-spice
  A pipelined RISCV implementation in VHDL
  ☆96Updated 6 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆179Updated 6 months ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆129Updated last year
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆308Updated 2 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆153Updated 7 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆166Updated 4 years ago
• Wolfgang-Spraul / fpgatools
  public domain tools for FPGAs
  ☆327Updated 8 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆275Updated 10 months ago
• forflo / yodl
  A VHDL frontend for Yosys
  ☆102Updated 8 years ago
• RobertBaruch / plugh-1
  A CPU on an FPGA that you can play Zork on
  ☆49Updated 8 years ago
• nullobject / sdram-fpga
  A FPGA core for a simple SDRAM controller.
  ☆119Updated 3 years ago
• zhemao / ez8
  The Easy 8-bit Processor
  ☆183Updated 11 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• alangarf / apple-one
  An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
  ☆143Updated last year
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆58Updated 7 years ago
• zylin / zpu
  The Zylin ZPU
  ☆244Updated 10 years ago
• cliffordwolf / SimpleVOut
  A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
  ☆239Updated 6 years ago
• makestuff / libfpgalink
  LIB:Library for interacting with an FPGA over USB
  ☆84Updated 4 years ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆170Updated 9 years ago
• knielsen / ice40_viewer
  ☆60Updated last year
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• matt-kimball / toygpu
  A simple GPU on a TinyFPGA BX
  ☆81Updated 6 years ago
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆178Updated 3 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆82Updated last year
• nesl / ice40_examples
  Public examples of ICE40 HX8K examples using Icestorm
  ☆110Updated 2 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 9 months ago