Domipheus / ArtyS7-RPU-SoC

Related projects ⓘ

Alternatives and complementary repositories for ArtyS7-RPU-SoC

• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆76Updated 4 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆79Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 5 months ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆82Updated 6 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆85Updated 4 years ago
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆74Updated last year
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆58Updated 5 years ago
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆36Updated 4 years ago
• sam210723 / fpga
  Collection of projects for various FPGA development boards
  ☆42Updated 6 months ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆33Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆52Updated 3 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆36Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆83Updated last month
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆83Updated 8 months ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆92Updated last year
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆40Updated 7 months ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆114Updated 8 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆47Updated 11 months ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆48Updated last month
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆73Updated 10 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆71Updated 2 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆111Updated 3 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆36Updated 10 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆64Updated 2 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆39Updated 2 weeks ago