Domipheus / ArtyS7-RPU-SoCLinks
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
☆39Updated 4 years ago
Alternatives and similar repositories for ArtyS7-RPU-SoC
Users that are interested in ArtyS7-RPU-SoC are comparing it to the libraries listed below
Sorting:
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 6 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- A wishbone controlled scope for FPGA's☆82Updated last year
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Minimal DVI / HDMI Framebuffer☆82Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- ☆22Updated 3 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Demo SoC for SiliconCompiler.☆59Updated 3 weeks ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆147Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- ☆41Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆59Updated last month
- Small footprint and configurable SPI core☆42Updated last week
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- Spen's Official OpenOCD Mirror☆50Updated 3 months ago
- Another tiny RISC-V implementation☆56Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆61Updated 3 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆42Updated 4 years ago
- A pipelined RISC-V processor☆57Updated last year
- Miscellaneous ULX3S examples (advanced)☆78Updated last week
- Collection of projects for various FPGA development boards☆45Updated last year