Domipheus / ArtyS7-RPU-SoC

Related projects: ⓘ

• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆78Updated 4 years ago
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆32Updated 5 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆84Updated 4 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆63Updated 2 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆74Updated 4 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆57Updated last month
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆74Updated 10 months ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆72Updated 8 months ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆39Updated 5 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆34Updated 3 months ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆58Updated 5 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆80Updated 6 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆63Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆34Updated 2 years ago
• sam210723 / fpga
  Collection of projects for various FPGA development boards
  ☆39Updated 4 months ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆92Updated last year
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆111Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆82Updated 6 months ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆45Updated 6 months ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆75Updated 2 weeks ago
• olofk / observer
  ☆40Updated 4 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 2 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆113Updated 8 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆34Updated last year
• projf / fpgatools
  Tools for FPGA development.
  ☆43Updated last year
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆36Updated 4 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆70Updated 2 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆33Updated 8 months ago