Domipheus / ArtyS7-RPU-SoCLinks
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
☆39Updated 4 years ago
Alternatives and similar repositories for ArtyS7-RPU-SoC
Users that are interested in ArtyS7-RPU-SoC are comparing it to the libraries listed below
Sorting:
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆149Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆93Updated 5 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆62Updated 6 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- A wishbone controlled scope for FPGA's☆83Updated last year
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Wishbone interconnect utilities☆41Updated 6 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- A FPGA core for a simple SDRAM controller.☆121Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- Nitro USB FPGA core☆87Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆176Updated last year
- USB Serial on the TinyFPGA BX☆137Updated 4 years ago
- An Open Source configuration of the Arty platform☆131Updated last year
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 6 years ago
- Source code to accompany https://timetoexplore.net☆63Updated 5 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆44Updated 4 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆97Updated 5 years ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 5 months ago
- VHDL library 4 FPGAs☆181Updated last week
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- SoftCPU/SoC engine-V☆54Updated 5 months ago