Digilent / Nexys-A7
☆15Updated 8 months ago
Alternatives and similar repositories for Nexys-A7:
Users that are interested in Nexys-A7 are comparing it to the libraries listed below
- Verilog implementation of multi-stage 32-bit RISC-V processor☆95Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated 2 weeks ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆72Updated last year
- This repo provide an index of VLSI content creators and their materials☆147Updated 7 months ago
- UVM and System Verilog Manuals☆40Updated 6 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Verilog HDL files☆128Updated 10 months ago
- ☆151Updated 2 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆36Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆42Updated 8 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆84Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆49Updated last year
- ☆14Updated last year
- SystemVerilog Tutorial☆138Updated this week
- A Single Cycle Risc-V 32 bit CPU☆40Updated 2 years ago
- ☆17Updated last year
- opensource EDA tool flor VLSI design☆32Updated last year
- Lecture about FIR filter on an FPGA☆11Updated 10 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 4 months ago
- ☆89Updated last year
- Static Timing Analysis Full Course☆52Updated 2 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆125Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago
- Pipelined RISC-V RV32I Core in Verilog☆38Updated last year
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 11 months ago
- ☆10Updated 2 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Updated 4 months ago