Digilent / Nexys-A7Links
☆15Updated 5 months ago
Alternatives and similar repositories for Nexys-A7
Users that are interested in Nexys-A7 are comparing it to the libraries listed below
Sorting:
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆168Updated 4 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆159Updated 5 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆82Updated 2 years ago
- 2014 UCSC Extension FPGA class☆20Updated 10 years ago
- Verilog HDL files☆170Updated last year
- SystemVerilog language-oriented exercises☆139Updated this week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆131Updated 10 years ago
- SystemVerilog Tutorial☆190Updated 2 months ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆570Updated 3 years ago
- Opensource DDR3 Controller☆413Updated 2 weeks ago
- ☆117Updated 2 years ago
- A Single Cycle Risc-V 32 bit CPU☆65Updated 2 weeks ago
- This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of …☆30Updated 2 years ago
- Design Verification Engineer interview preparation guide.☆43Updated 6 months ago
- All code found on nandland is here. underconstruction.gif☆358Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- This repo provide an index of VLSI content creators and their materials☆164Updated last year
- 100 Days of RTL☆406Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆128Updated 3 years ago
- WISHBONE SD Card Controller IP Core☆130Updated 3 years ago
- Verilog UART☆192Updated 12 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆134Updated 4 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆290Updated 8 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆125Updated 5 years ago
- An overview of TL-Verilog resources and projects☆82Updated last month
- SPI Master for FPGA - VHDL and Verilog☆322Updated 2 years ago
- opensource EDA tool flor VLSI design☆36Updated 2 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆196Updated last week