jswtyc / SystemVerilog_UARTView external linksLinks
The best rtl_uart in github! This is a UART design based on AXI Stream/Ready Vallid protocol. Support parameterized data bit width, clock frequency, baud rate, and parity check.
☆11May 8, 2025Updated 9 months ago
Alternatives and similar repositories for SystemVerilog_UART
Users that are interested in SystemVerilog_UART are comparing it to the libraries listed below
Sorting:
- ☆27Sep 16, 2025Updated 4 months ago
- ☆12Mar 19, 2025Updated 10 months ago
- A high-performance C++20 cache simulator with power/area modeling, MESI coherence, prefetching, and multi-level hierarchy support for arc…☆12Updated this week
- Driver for EL320.240.36 using an RP2040 or STM32☆10Jan 20, 2024Updated 2 years ago
- ☆27Apr 26, 2020Updated 5 years ago
- ☆18May 5, 2022Updated 3 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆13Jun 24, 2022Updated 3 years ago
- ☆12May 21, 2020Updated 5 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 5 months ago
- A cycle accurate emulator for the 6502 microprocessor☆17Oct 1, 2023Updated 2 years ago
- Qemu tracing plugin using SimPoints☆17Sep 12, 2024Updated last year
- CPU Emulator for ARMv7☆15Jun 7, 2022Updated 3 years ago
- 基于树莓派3构建一个操作系统的系列教程☆13Jun 19, 2018Updated 7 years ago
- A simple javascript timer for timelog form☆30Dec 21, 2012Updated 13 years ago
- NoC simulation using gem5 (a simple tul)☆14Mar 23, 2024Updated last year
- SoC design & prototyping☆16Jun 13, 2025Updated 8 months ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆18Jun 24, 2021Updated 4 years ago
- ☆17Dec 13, 2014Updated 11 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆15Mar 23, 2022Updated 3 years ago
- Brain is a system to model, create and manage the knowledge base of chatbots based on AIML technology.☆19Mar 9, 2018Updated 7 years ago
- Cycle-accurate ARMv6-M simulator☆16Feb 9, 2018Updated 8 years ago
- Universal firmware for CNC machines☆18Feb 28, 2016Updated 9 years ago
- E-ink wireless display☆15Oct 4, 2016Updated 9 years ago
- This is where gem5 based DRAM cache models live.☆20Mar 23, 2023Updated 2 years ago
- ARM Assembler Editor and Simulator written in C++ with QT5 and ANTLR 4.8☆15Jun 15, 2020Updated 5 years ago
- Instrumentation CPU profiler for Linux and macOS applications☆22Mar 22, 2025Updated 10 months ago
- use two version gem5 to create spec2006 cpu simpoint & checkpoint☆16Oct 19, 2019Updated 6 years ago
- A transaction level model of a PCI express root complex implemented in systemc☆23Jun 16, 2014Updated 11 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Dec 3, 2020Updated 5 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- making a GUI-Based Employee Management System using SQLite 3 and Pyqt5☆20Oct 15, 2021Updated 4 years ago
- A python parser for decoding arm aarch32 and aarch64 system registers☆24Aug 10, 2023Updated 2 years ago
- An standalone execution trace library built on DynamoRIO.☆23Jul 4, 2022Updated 3 years ago
- A simple processor implemented in SystemC☆26Dec 10, 2016Updated 9 years ago
- ☆22Mar 14, 2023Updated 2 years ago
- A cycle-accurate CPU emulator of the MOS Technology 65xx series☆24Sep 11, 2025Updated 5 months ago
- ARMv8 example programs to learn from and armsim, an ARMv8 simulator☆23Oct 6, 2025Updated 4 months ago
- Trace Log Generation (CLI) on a target device or emulator : Generating context information of every instruction from a specific point (in…☆22Jan 16, 2017Updated 9 years ago