gzhy5111 / cpuLinks
《自己动手写CPU》
☆20Updated 4 years ago
Alternatives and similar repositories for cpu
Users that are interested in cpu are comparing it to the libraries listed below
Sorting:
- NUDT 高级体系结构实验☆35Updated last year
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆147Updated last year
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆182Updated 4 years ago
- 一生一芯的信息发布和内容网站☆136Updated 2 years ago
- NJU Virtual Board☆299Updated 5 months ago
- ☆42Updated 2 years ago
- ☆161Updated last month
- ☆92Updated 4 months ago
- 中国科学院大学高级计算机体系结构课程作业:使用OpenROAD-flow完成RTL到GDS全流程☆30Updated 5 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- ☆127Updated 3 years ago
- ☆66Updated last year
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆86Updated 6 years ago
- ☆104Updated 2 months ago
- 《自己动手写CPU》一书附带的文件☆87Updated 7 years ago
- "aura" my super-scalar O3 cpu core☆25Updated last year
- ☆72Updated 2 years ago
- ☆35Updated 6 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Updated 9 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆34Updated 4 years ago
- CQU Dual Issue Machine☆38Updated last year
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆134Updated 5 years ago
- NSCSCC 信息整合☆251Updated 4 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Updated last month
- ☆90Updated 2 months ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆30Updated last year
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆18Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆62Updated last year