verimake-team / MLonFPGALinks
A series of mainstream machine learning algorithms implement on FPGA.
☆13Updated 4 years ago
Alternatives and similar repositories for MLonFPGA
Users that are interested in MLonFPGA are comparing it to the libraries listed below
Sorting:
- Verilog based BCH encoder/decoder☆128Updated 3 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆75Updated last year
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- UART -> AXI Bridge☆67Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Verilog digital signal processing components☆161Updated 3 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆126Updated 3 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago
- 视频旋转(2019FPGA大赛)☆37Updated 5 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- AES加密解密算法的Verilog实现☆67Updated 9 years ago
- I2C controller core☆47Updated 2 years ago
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆81Updated 5 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆158Updated 9 months ago
- SPI Slave for FPGA in Verilog and VHDL☆217Updated last year
- use Verilog HDL implemente bicubic interpolation in FPGA☆29Updated 5 years ago
- AHB3-Lite Interconnect☆107Updated last year
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆146Updated 2 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆77Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Gigabit Ethernet UDP communication driver☆80Updated 6 years ago
- Pipeline FFT Implementation in Verilog HDL☆149Updated 6 years ago
- AMBA bus generator including AXI, AHB, and APB☆115Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆89Updated last year
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Verilog UART☆186Updated 12 years ago
- H264视频解码verilog实现☆85Updated 8 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- AES hardware engine for Xilinx Zynq platform☆32Updated 4 years ago