HUST-OS / design-pattern-notes
各类内核的设计思路
☆19Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for design-pattern-notes
- 洛佳的异步内核实验室☆25Updated 3 years ago
- 调试大师:你见过最强的内核调试器☆35Updated 3 years ago
- ☆30Updated last year
- 快速陷入处理☆32Updated last year
- 自嗨虚拟化软件 - 'Enjoy yourself' type-1 hypervisor software☆25Updated 2 years ago
- 在RISC-V处理器上实现一个轻量级的Hypervisor。☆12Updated 3 years ago
- Low level access to RISCV processors☆19Updated 2 years ago
- Asynchronous OS kernel written in Rust.☆33Updated 3 years ago
- 用Rust语言重新设计与实现xv6☆35Updated 2 years ago
- A Rust based Multicore OS developed by UltraTeam, HITsz. Currently updated on https://gitee.com/LoanCold/ultraos_backup☆45Updated 5 months ago
- Rust support for RISC-V Platform-Level Interrupt Controller☆10Updated 2 years ago
- An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.☆49Updated 2 years ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆30Updated 2 years ago
- ☆13Updated 3 years ago
- 洛佳的异步内核实验室,第二版☆13Updated 3 years ago
- OS Tutorial Summer of Code 2020☆19Updated 2 years ago
- [WIP] Tutorial for zCore kernel.☆57Updated 3 years ago
- [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)☆14Updated 4 years ago
- 遍历设备树二进制对象☆12Updated 11 months ago
- 实现和扩展RISC-V SBI运行时,使之能够支持并运行操作系统☆14Updated 2 years ago
- ☆22Updated 2 years ago
- zcore_tutorial文档撰写工作以及单元测试工作组☆19Updated 4 years ago
- 没分支的 rCore-Tutorial☆44Updated last year
- An RISC-V experimental OS☆25Updated last year
- Serialize & deserialize device tree binary using serde☆21Updated last week
- Simple RISC-V SBI runtime library; designated for supervisor use☆21Updated 10 months ago
- Low level access to T-Head Xuantie RISC-V processors☆32Updated 2 years ago
- YCSB in Rust (WIP)☆19Updated 3 years ago
- A simple lua jit implemented in Rust for HUST-Complier principle course.☆12Updated 3 years ago
- The Decaf compiler, written in Rust☆56Updated 4 years ago