were / bfsh

Related projects ⓘ

Alternatives and complementary repositories for bfsh

• yhtzd / skyloft
  Skyloft: A General High-Efficient Scheduling Framework in User Space (SOSP 2024)
  ☆22Updated 2 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• uwplse / rake
  compiling DSLs to high-level hardware instructions
  ☆21Updated 2 years ago
• efeslab / moesi-prime
  ☆14Updated last year
• JohndeVostok / APE
  A GPU FP32 computation method with Tensor Cores.
  ☆18Updated 2 years ago
• gty111 / PTX-EMU
  PTX-EMU is a simple emulator for CUDA program.
  ☆24Updated 10 months ago
• miaochenlu / Gem5_tutorials
  ☆17Updated last year
• Jiacheng / honeycomb-osdi23-ae
  ☆13Updated last year
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆10Updated 7 months ago
• SwarmArch / T4
  Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"
  ☆27Updated 2 years ago
• CMU-SAFARI / Virtuoso
  Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.
  ☆25Updated last year
• ychen306 / vegen
  ☆27Updated last year
• fpgasystems / hacc
  ETHZ Heterogeneous Accelerated Compute Cluster.
  ☆29Updated last month
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 4 years ago
• oscomp / proj6-user-level-interrupt
  基于FPGA实现用户态中断硬件机制与优化操作系统内核
  ☆9Updated 10 months ago
• regehr / pldi22-llvm-tutorial
  outline and links for PLDI 2022 tutorial
  ☆17Updated 2 years ago
• WukLab / FPGA-OS
  ☆32Updated 3 years ago
• dskarlatos / ElasticCuckooHashing
  (elastic) cuckoo hashing
  ☆13Updated 4 years ago
• heterorefactor / heterorefactor
  HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA
  ☆10Updated 3 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆28Updated last week
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆40Updated last year
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆33Updated 3 years ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆17Updated last week
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆30Updated 2 years ago
• zzrcxb / PinnedLoads
  Gem5 implementation of Pinned Loads: Taming Speculative Loads in Secure Processors
  ☆9Updated 2 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• aakahlow / gem5Valid_Haswell
  ☆18Updated 4 years ago