Charlie5DH / RISC-V-Single-Cycle-uPLinks
Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture
☆13Updated 5 years ago
Alternatives and similar repositories for RISC-V-Single-Cycle-uP
Users that are interested in RISC-V-Single-Cycle-uP are comparing it to the libraries listed below
Sorting:
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Updated last week
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Updated 6 years ago
- An implementation of RISC-V☆47Updated last month
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated last week
- Simple 8-bit UART realization on Verilog HDL.☆114Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 7 months ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated last week
- Naive Educational RISC V processor☆94Updated 3 months ago
- Verilog implementation of a RISC-V core☆135Updated 7 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆97Updated 11 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆109Updated 4 years ago
- RISC-V Nox core☆71Updated 6 months ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated 3 weeks ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- few python scripts to clone all IP cores from opencores.org☆26Updated 2 years ago
- Another tiny RISC-V implementation☆64Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- 64-bit multicore Linux-capable RISC-V processor☆105Updated 9 months ago
- MR1 formally verified RISC-V CPU☆57Updated 7 years ago
- A Risc-V SoC for Tiny Tapeout☆47Updated 2 months ago
- Simple RiscV core for academic purpose.☆23Updated 5 years ago
- A simple implementation of a UART modem in Verilog.☆173Updated 4 years ago
- Spen's Official OpenOCD Mirror☆51Updated 11 months ago
- Optimized RISC-V FP emulation for 32-bit processors☆36Updated 4 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Updated last week