Alternatives and similar repositories for RISC-V-Single-Cycle-uP:

Users that are interested in RISC-V-Single-Cycle-uP are comparing it to the libraries listed below

• ATaylorCEngFIET / introduction_to_vivado
  ☆20Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆66Updated this week
• agra-uni-bremen / riscv-freertos
  FreeRTOS port for the RISC-V Virtual Prototype
  ☆14Updated 4 years ago
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 4 years ago
• open-design / riscv-soc-cores
  ☆37Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 3 weeks ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆80Updated this week
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆25Updated last year
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆45Updated 5 months ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆26Updated 4 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆48Updated last month
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆45Updated last year
• vsdip / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆16Updated 4 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆75Updated last year
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆36Updated 2 months ago
• sudhamshu091 / Hardware-Description-Languages-for-FPGA-Design
  My HDL activities appear here. This is for my personal use. PPT's copyrights to University of Colorado Boulder.
  ☆16Updated 4 years ago
• fabriziotappero / opencores-scraper
  few python scripts to clone all IP cores from opencores.org
  ☆21Updated last year
• vlsiexcellence / Verilog-Crash-Course
  Verilog Fundamentals Explained for Beginners and Professionals
  ☆21Updated 2 years ago
• nematoli / SPI-FPGA-VHDL
  SPI Master and Slave components to be used in all of FPGAs, written in VHDL.
  ☆36Updated 5 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆42Updated 4 years ago
• vfinotti / cortex-m0-soft-microcontroller
  Soft-microcontroller implementation of an ARM Cortex-M0
  ☆25Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆36Updated 3 years ago
• HDLForBeginners / Examples
  ☆92Updated last year
• arthurbeggs / riscv-simple
  Computer architecture learning environment using FPGAs
  ☆13Updated 3 years ago
• jiacaiyuan / i2c_slave
  I2C slave Verilog Design and TestBench
  ☆21Updated 5 years ago
• stnolting / riscv-debug-dtm
  🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
  ☆26Updated 2 years ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆19Updated 2 months ago
• aesc-silicon / i2c-gpio-expander
  End-to-End Open-Source I2C GPIO Expander
  ☆31Updated 3 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆73Updated this week