Charlie5DH / RISC-V-Single-Cycle-uPLinks
Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture
☆12Updated 5 years ago
Alternatives and similar repositories for RISC-V-Single-Cycle-uP
Users that are interested in RISC-V-Single-Cycle-uP are comparing it to the libraries listed below
Sorting:
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 11 months ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Updated 6 years ago
- RISC-V Nox core☆68Updated 2 months ago
- An implementation of RISC-V☆42Updated 3 weeks ago
- Naive Educational RISC V processor☆89Updated this week
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆18Updated 4 months ago
- A Risc-V SoC for Tiny Tapeout☆39Updated 2 weeks ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆27Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆20Updated 3 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated this week
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.