Alternatives and similar repositories for RISC-V-Single-Cycle-uP

Users that are interested in RISC-V-Single-Cycle-uP are comparing it to the libraries listed below

• schoeberl / wildcat
  An implementation of RISC-V
  ☆44Updated last week
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆51Updated last year
• ZiCog / sodor-spinal
  An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.
  ☆14Updated 6 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆37Updated this week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆92Updated 2 months ago
• aignacio / nox
  RISC-V Nox core
  ☆70Updated 4 months ago
• dpretet / friscv
  RISCV CPU implementation in SystemVerilog
  ☆32Updated 2 months ago
• jeras / rp32
  RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
  ☆20Updated 3 weeks ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆109Updated this week
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆38Updated 11 months ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated 4 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆102Updated 2 weeks ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆106Updated 4 years ago
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆23Updated 5 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆111Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆76Updated 2 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆48Updated last week
• NayanaBannur / 8-bit-RISC-Processor
  A Verilog RTL model of a simple 8-bit RISC processor
  ☆15Updated 6 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆54Updated 2 years ago
• agra-uni-bremen / riscv-freertos
  FreeRTOS port for the RISC-V Virtual Prototype
  ☆14Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 9 months ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆62Updated 4 years ago
• MichaelBell / tinyQV
  A Risc-V SoC for Tiny Tapeout
  ☆43Updated 2 weeks ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆133Updated 7 years ago
• leonow32 / verilog-fpga
  Many peripherals in Verilog ready to use
  ☆40Updated 11 months ago
• vfinotti / cortex-m0-soft-microcontroller
  Soft-microcontroller implementation of an ARM Cortex-M0
  ☆26Updated 6 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 5 months ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆42Updated 2 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆70Updated 3 years ago