Source code & scripts for experimental characterization and demonstration of performing NOT and up to 16-input AND, NAND, OR, and NOR operations in real DDR4 DRAM chips. Described in our HPCA'24 paper by Yuksel et al. at https://arxiv.org/abs/2402.18736
☆16Apr 9, 2024Updated 2 years ago
Alternatives and similar repositories for FCDRAM
Users that are interested in FCDRAM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper h…☆11Jan 23, 2026Updated 6 months ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆18Aug 2, 2019Updated 7 years ago
- Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input maj…☆18May 17, 2024Updated 2 years ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 4 years ago
- New RowHammer mitigation mechanism that is area-, performance-, and energy-efficient especially at very low (e.g., 125) RowHammer thresho…☆17May 2, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆15Sep 24, 2020Updated 5 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆37Oct 23, 2023Updated 2 years ago
- pLUTo is a DRAM-based Processing-using-Memory architecture that leverages the high density of DRAM to enable the massively parallel stori…☆20Jan 12, 2023Updated 3 years ago
- Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Proc…☆31Sep 12, 2025Updated 10 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆80Dec 11, 2023Updated 2 years ago
- Source code of the U-TRR methodology presented in "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHamme…☆18Nov 15, 2022Updated 3 years ago
- Source code & scripts for experimental characterization and real-system demonstration of RowPress, a widespread read disturbance phenomen…☆42Jan 11, 2024Updated 2 years ago
- Succinct C++☆24Sep 13, 2020Updated 5 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆49May 25, 2024Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- PyGim is the first runtime framework to efficiently execute Graph Neural Networks (GNNs) on real Processing-in-Memory systems. It provide…☆36Apr 23, 2025Updated last year
- Dysl-vla:Official code for "DySL-VLA: Efficient Vision-Language-Action Model Inference via Dynamic-Static Layer-Skipping for Robot Manipu…☆25Jul 9, 2026Updated last month
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 4 years ago
- A tool for formally verifying constant-time software against hardware 🕰️☆16Feb 1, 2025Updated last year
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast See…☆11Feb 5, 2018Updated 8 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆14Aug 23, 2024Updated last year
- Source code for the software implementations of the GenASM algorithms proposed in our MICRO 2020 paper: Senol Cali et. al., "GenASM: A Hi…☆32Dec 19, 2022Updated 3 years ago
- ☆14Dec 15, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆92Aug 3, 2026Updated last week
- GenStore is the first in-storage processing system designed for genome sequence analysis that greatly reduces both data movement and comp…☆15Apr 6, 2022Updated 4 years ago
- Hook Metin2 PyRun_SimpleStringFlags DUMPER for python based cheats to metin2☆15Sep 16, 2021Updated 4 years ago
- This simulator models multi core systems with primary focus on the memory hierarchy. It models a trace-based out-of-order core frontend a…☆12Feb 12, 2016Updated 10 years ago
- MICRO 2023 Evaluation Artifact for TeAAL☆11Oct 26, 2023Updated 2 years ago
- This repository is for sharing code and information related to researching the "rowhammer" problem with respect to GPUs.☆15Apr 20, 2017Updated 9 years ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆145May 3, 2025Updated last year
- Ariadne is a new compressed swap scheme for mobile devices that reduces application relaunch latency and CPU usage while increasing the n…☆15Feb 19, 2025Updated last year
- Model, design, and explore tensor algebra accelerators.☆37Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆41Mar 1, 2019Updated 7 years ago
- Repository for the current status of the LESS submission☆12Jul 15, 2026Updated 3 weeks ago
- HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). It is released with the DASH memory scheduler…☆19Jan 11, 2016Updated 10 years ago
- Source code for the cycle-level simulator and RTL implementation of BlockHammer proposed in our HPCA 2021 paper: Yaglikci et. al., "Block…☆18Jun 17, 2022Updated 4 years ago
- NATSA is the first near-data-processing accelerator for time series analysis based on the Matrix Profile (SCRIMP) algorithm. NATSA exploi…☆17Jun 14, 2023Updated 3 years ago
- TransPimLib is a library for transcendental (and other hard-to-calculate) functions in general-purpose PIM systems, TransPimLib provides …☆15Apr 21, 2023Updated 3 years ago