Alternatives and similar repositories for U-TRR

Users that are interested in U-TRR are comparing it to the libraries listed below

• CMU-SAFARI / DRAM-Bender
  DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…
  ☆89Updated last month
• cwfletcher / stt
  ☆35Updated 4 years ago
• CMU-SAFARI / SoftMC
  SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…
  ☆136Updated last year
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆60Updated 5 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆64Updated 5 years ago
• CMU-SAFARI / BlockHammer
  Source code for the cycle-level simulator and RTL implementation of BlockHammer proposed in our HPCA 2021 paper: Yaglikci et. al., "Block…
  ☆18Updated 3 years ago
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 5 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆23Updated last year
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated last month
• antmicro / rowhammer-tester
  ☆64Updated 3 months ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 4 years ago
• Yujie-Cui / WB-channels
  ☆12Updated 3 years ago
• bring-your-own-core / byoc
  The OpenPiton Platform
  ☆29Updated 2 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆27Updated 2 years ago
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆51Updated 2 months ago
• efeslab / dolma
  ☆13Updated 4 years ago
• CMU-SAFARI / ABACuS
  New RowHammer mitigation mechanism that is area-, performance-, and energy-efficient especially at very low (e.g., 125) RowHammer thresho…
  ☆15Updated last year
• darchr / parsec-benchmark
  ☆17Updated 4 years ago
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆74Updated 2 weeks ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆22Updated 2 years ago
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆33Updated 5 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆69Updated 4 months ago
• darchr / gem5art
  Artifact, reproducibility, and testing utilites for gem5
  ☆22Updated 4 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆55Updated last month
• darchr / gem5-skylake-config
  gem5 configuration for intel's skylake micro-architecture
  ☆51Updated 3 years ago
• 0xd3ba / build-your-own-prefetcher
  This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator
  ☆37Updated 3 years ago
• Errare-humanum-est / ProtoGen
  Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…
  ☆16Updated 3 years ago